If the UART bus or baud clock has a gate, it must be enabled before the
UART can be used.
Series-to: Tom Rini <trini@konsulko.com>
Series-cc: Stefan Roese <sr@denx.de>
Series-cc: Simon Glass <sjg@chromium.org>
Series-cc: u-boot@lists.denx.de
Series-prefix: RESEND
Series-version: 3
Series-changes: 2
- Only enable the first clock, as using the clk_get_bulk() API pushes
a board (phycore-rk3288) over its SPL size limit.
Series-changes: 3
- Switch back to the original patch, now that the phycore-rk3288 build
is fixed by enabling LTO.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>