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cd06e60c44
Move gpio-controller up to pinctrl node and rename label to "pio" to match the label used in upstream kernel linux. Update any DTS that reference the pinctrl to follow the new naming and structure. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Weijie Gao <weijie.gao@mediatek.com> Tested-by: Weijie Gao <weijie.gao@mediatek.com>
644 lines
17 KiB
Plaintext
644 lines
17 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt7988-clk.h>
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#include <dt-bindings/reset/mt7988-reset.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/mt65xx.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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compatible = "mediatek,mt7988-rfb";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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reg = <0x0>;
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mediatek,hwver = <&hwver>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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reg = <0x1>;
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mediatek,hwver = <&hwver>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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reg = <0x2>;
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mediatek,hwver = <&hwver>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a73";
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reg = <0x3>;
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mediatek,hwver = <&hwver>;
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};
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};
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system_clk: dummy40m {
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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#clock-cells = <0>;
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};
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spi_clk: dummy208m {
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compatible = "fixed-clock";
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clock-frequency = <208000000>;
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#clock-cells = <0>;
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};
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hwver: hwver {
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compatible = "mediatek,hwver", "syscon";
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reg = <0 0x8000000 0 0x1000>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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clock-frequency = <13000000>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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watchdog: watchdog@1001c000 {
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compatible = "mediatek,mt7622-wdt",
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"mediatek,mt6589-wdt",
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"syscon";
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reg = <0 0x1001c000 0 0x1000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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#reset-cells = <1>;
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};
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0 0x0c000000 0 0x40000>, /* GICD */
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<0 0x0c080000 0 0x200000>; /* GICR */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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apmixedsys: apmixedsys@1001e000 {
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compatible = "mediatek,mt7988-fixed-plls", "syscon";
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reg = <0 0x1001e000 0 0x1000>;
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#clock-cells = <1>;
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};
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topckgen: topckgen@1001b000 {
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compatible = "mediatek,mt7988-topckgen", "syscon";
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reg = <0 0x1001b000 0 0x1000>;
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clock-parent = <&apmixedsys>;
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#clock-cells = <1>;
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};
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pio: pinctrl@1001f000 {
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compatible = "mediatek,mt7988-pinctrl";
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reg = <0 0x1001f000 0 0x1000>,
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<0 0x11c10000 0 0x1000>,
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<0 0x11d00000 0 0x1000>,
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<0 0x11d20000 0 0x1000>,
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<0 0x11e00000 0 0x1000>,
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<0 0x11f00000 0 0x1000>,
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<0 0x1000b000 0 0x1000>;
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reg-names = "gpio", "iocfg_tr", "iocfg_br",
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"iocfg_rb", "iocfg_lb", "iocfg_tl",
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"eint";
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gpio-controller;
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#gpio-cells = <2>;
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};
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sgmiisys0: syscon@10060000 {
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compatible = "mediatek,mt7988-sgmiisys_0", "syscon";
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reg = <0 0x10060000 0 0x1000>;
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clock-parent = <&topckgen>;
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#clock-cells = <1>;
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};
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sgmiisys1: syscon@10070000 {
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compatible = "mediatek,mt7988-sgmiisys_1", "syscon";
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reg = <0 0x10070000 0 0x1000>;
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clock-parent = <&topckgen>;
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#clock-cells = <1>;
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};
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usxgmiisys0: syscon@10080000 {
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compatible = "mediatek,mt7988-usxgmiisys_0", "syscon";
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reg = <0 0x10080000 0 0x1000>;
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clock-parent = <&topckgen>;
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#clock-cells = <1>;
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};
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usxgmiisys1: syscon@10081000 {
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compatible = "mediatek,mt7988-usxgmiisys_1", "syscon";
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reg = <0 0x10081000 0 0x1000>;
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clock-parent = <&topckgen>;
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#clock-cells = <1>;
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};
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dummy_clk: dummy12m {
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compatible = "fixed-clock";
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clock-frequency = <12000000>;
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#clock-cells = <0>;
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/* must need this line, or uart uanable to get dummy_clk */
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bootph-all;
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};
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xhci1: xhci@11200000 {
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compatible = "mediatek,mt7988-xhci",
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"mediatek,mtk-xhci";
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reg = <0 0x11200000 0 0x2e00>,
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<0 0x11203e00 0 0x0100>;
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reg-names = "mac", "ippc";
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interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&tphyu2port0 PHY_TYPE_USB2>,
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<&tphyu3port0 PHY_TYPE_USB3>;
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clocks = <&dummy_clk>,
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<&dummy_clk>,
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<&dummy_clk>,
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<&dummy_clk>,
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<&dummy_clk>;
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clock-names = "sys_ck",
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"xhci_ck",
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"ref_ck",
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"mcu_ck",
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"dma_ck";
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#address-cells = <2>;
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#size-cells = <2>;
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status = "okay";
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};
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pcie2: pcie@11280000 {
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compatible = "mediatek,mt7988-pcie",
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"mediatek,mt7986-pcie",
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"mediatek,mt8192-pcie";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0 0x11280000 0 0x2000>;
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reg-names = "pcie-mac";
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linux,pci-domain = <3>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x20200000 0 0x20200000 0 0x07e00000>;
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clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
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<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
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<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
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<&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
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clock-names = "pl_250m", "tl_26m", "peri_26m",
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"top_133m";
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phys = <&xphyu3port0 PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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status = "disabled";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &pcie_intc2 0>,
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<0 0 0 2 &pcie_intc2 1>,
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<0 0 0 3 &pcie_intc2 2>,
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<0 0 0 4 &pcie_intc2 3>;
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pcie_intc2: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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pcie3: pcie@11290000 {
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compatible = "mediatek,mt7988-pcie",
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"mediatek,mt7986-pcie",
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"mediatek,mt8192-pcie";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0 0x11290000 0 0x2000>;
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reg-names = "pcie-mac";
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linux,pci-domain = <2>;
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interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x28200000 0 0x28200000 0 0x07e00000>;
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clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
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<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
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<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
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<&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
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clock-names = "pl_250m", "tl_26m", "peri_26m",
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"top_133m";
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use-dedicated-phy;
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status = "disabled";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &pcie_intc3 0>,
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<0 0 0 2 &pcie_intc3 1>,
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<0 0 0 3 &pcie_intc3 2>,
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<0 0 0 4 &pcie_intc3 3>;
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pcie_intc3: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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pcie0: pcie@11300000 {
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compatible = "mediatek,mt7988-pcie",
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"mediatek,mt7986-pcie",
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"mediatek,mt8192-pcie";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0 0x11300000 0 0x2000>;
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reg-names = "pcie-mac";
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linux,pci-domain = <0>;
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interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x30200000 0 0x30200000 0 0x07e00000>;
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clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
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<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
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<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
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<&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
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clock-names = "pl_250m", "tl_26m", "peri_26m",
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"top_133m";
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use-dedicated-phy;
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status = "disabled";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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<0 0 0 3 &pcie_intc0 2>,
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<0 0 0 4 &pcie_intc0 3>;
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pcie_intc0: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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pcie1: pcie@11310000 {
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compatible = "mediatek,mt7988-pcie",
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"mediatek,mt7986-pcie",
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"mediatek,mt8192-pcie";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0 0x11310000 0 0x2000>;
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reg-names = "pcie-mac";
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linux,pci-domain = <1>;
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interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x38200000 0 0x38200000 0 0x07e00000>;
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clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
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<&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
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<&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
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<&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
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clock-names = "pl_250m", "tl_26m", "peri_26m",
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"top_133m";
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use-dedicated-phy;
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status = "disabled";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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<0 0 0 3 &pcie_intc1 2>,
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<0 0 0 4 &pcie_intc1 3>;
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pcie_intc1: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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usbtphy: usb-phy@11c50000 {
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compatible = "mediatek,mt7988",
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"mediatek,generic-tphy-v2";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "okay";
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tphyu2port0: usb-phy@11c50000 {
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reg = <0 0x11c50000 0 0x700>;
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clocks = <&dummy_clk>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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tphyu3port0: usb-phy@11c50700 {
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reg = <0 0x11c50700 0 0x900>;
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clocks = <&dummy_clk>;
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clock-names = "ref";
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#phy-cells = <1>;
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mediatek,usb3-pll-ssc-delta;
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mediatek,usb3-pll-ssc-delta1;
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status = "okay";
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};
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};
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xphy: xphy@11e10000 {
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compatible = "mediatek,mt7988", "mediatek,xsphy";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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xphyu3port0: usb-phy@11e13000 {
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reg = <0 0x11e13400 0 0x500>;
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clocks = <&dummy_clk>;
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clock-names = "ref";
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#phy-cells = <1>;
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status = "okay";
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};
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};
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xfi_pextp0: syscon@11f20000 {
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compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
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reg = <0 0x11f20000 0 0x10000>;
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clock-parent = <&topckgen>;
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#clock-cells = <1>;
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};
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xfi_pextp1: syscon@11f30000 {
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compatible = "mediatek,mt7988-xfi_pextp_1", "syscon";
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reg = <0 0x11f30000 0 0x10000>;
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clock-parent = <&topckgen>;
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#clock-cells = <1>;
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};
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xfi_pll: syscon@11f40000 {
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compatible = "mediatek,mt7988-xfi_pll", "syscon";
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reg = <0 0x11f40000 0 0x1000>;
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clock-parent = <&topckgen>;
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#clock-cells = <1>;
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};
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topmisc: topmisc@11d10000 {
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compatible = "mediatek,mt7988-topmisc", "syscon",
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"mediatek,mt7988-power-controller";
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reg = <0 0x11d10000 0 0x10000>;
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clock-parent = <&topckgen>;
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#clock-cells = <1>;
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};
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infracfg: infracfg@10001000 {
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compatible = "mediatek,mt7988-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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clock-parent = <&topckgen>;
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#clock-cells = <1>;
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};
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uart0: serial@11000000 {
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compatible = "mediatek,hsuart";
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reg = <0 0x11000000 0 0x100>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_52M_UART0_CK>;
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assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&infracfg CLK_INFRA_MUX_UART0_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
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<&topckgen CLK_TOP_UART_SEL>;
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status = "disabled";
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};
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uart1: serial@11000100 {
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compatible = "mediatek,hsuart";
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reg = <0 0x11000100 0 0x100>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_52M_UART1_CK>;
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assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&infracfg CLK_INFRA_MUX_UART1_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
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<&topckgen CLK_TOP_UART_SEL>;
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status = "disabled";
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};
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uart2: serial@11000200 {
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compatible = "mediatek,hsuart";
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reg = <0 0x11000200 0 0x100>;
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_52M_UART2_CK>;
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assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&infracfg CLK_INFRA_MUX_UART2_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
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<&topckgen CLK_TOP_UART_SEL>;
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status = "disabled";
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};
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i2c0: i2c@11003000 {
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compatible = "mediatek,mt7988-i2c",
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"mediatek,mt7981-i2c";
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reg = <0 0x11003000 0 0x1000>,
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<0 0x10217080 0 0x80>;
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-div = <1>;
|
|
clocks = <&infracfg CLK_INFRA_I2C_BCK>,
|
|
<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
|
|
clock-names = "main", "dma";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@11004000 {
|
|
compatible = "mediatek,mt7988-i2c",
|
|
"mediatek,mt7981-i2c";
|
|
reg = <0 0x11004000 0 0x1000>,
|
|
<0 0x10217100 0 0x80>;
|
|
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-div = <1>;
|
|
clocks = <&infracfg CLK_INFRA_I2C_BCK>,
|
|
<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
|
|
clock-names = "main", "dma";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@11005000 {
|
|
compatible = "mediatek,mt7988-i2c",
|
|
"mediatek,mt7981-i2c";
|
|
reg = <0 0x11005000 0 0x1000>,
|
|
<0 0x10217180 0 0x80>;
|
|
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-div = <1>;
|
|
clocks = <&infracfg CLK_INFRA_I2C_BCK>,
|
|
<&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
|
|
clock-names = "main", "dma";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm: pwm@10048000 {
|
|
compatible = "mediatek,mt7988-pwm";
|
|
reg = <0 0x10048000 0 0x1000>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
|
|
<&infracfg CLK_INFRA_66M_PWM_HCK>,
|
|
<&infracfg CLK_INFRA_66M_PWM_CK1>,
|
|
<&infracfg CLK_INFRA_66M_PWM_CK2>,
|
|
<&infracfg CLK_INFRA_66M_PWM_CK3>,
|
|
<&infracfg CLK_INFRA_66M_PWM_CK4>,
|
|
<&infracfg CLK_INFRA_66M_PWM_CK5>,
|
|
<&infracfg CLK_INFRA_66M_PWM_CK6>,
|
|
<&infracfg CLK_INFRA_66M_PWM_CK7>,
|
|
<&infracfg CLK_INFRA_66M_PWM_CK8>;
|
|
clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
|
|
"pwm4","pwm5","pwm6","pwm7","pwm8";
|
|
status = "disabled";
|
|
};
|
|
|
|
snand: snand@11001000 {
|
|
compatible = "mediatek,mt7988-snand",
|
|
"mediatek,mt7986-snand";
|
|
reg = <0 0x11001000 0 0x1000>,
|
|
<0 0x11002000 0 0x1000>;
|
|
reg-names = "nfi", "ecc";
|
|
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&infracfg CLK_INFRA_SPINFI>,
|
|
<&infracfg CLK_INFRA_NFI>,
|
|
<&infracfg CLK_INFRA_66M_NFI_HCK>;
|
|
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
|
|
assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
|
|
<&topckgen CLK_TOP_NFI1X_SEL>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
|
|
<&topckgen CLK_TOP_MPLL_D8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@1100a000 {
|
|
compatible = "mediatek,ipm-spi";
|
|
reg = <0 0x11007000 0 0x100>;
|
|
clocks = <&spi_clk>,
|
|
<&spi_clk>;
|
|
clock-names = "sel-clk", "spi-clk";
|
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@1100b000 {
|
|
compatible = "mediatek,ipm-spi";
|
|
reg = <0 0x11008000 0 0x100>;
|
|
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@11009000 {
|
|
compatible = "mediatek,ipm-spi";
|
|
reg = <0 0x11009000 0 0x100>;
|
|
clocks = <&spi_clk>,
|
|
<&spi_clk>;
|
|
clock-names = "sel-clk", "spi-clk";
|
|
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc0: mmc@11230000 {
|
|
compatible = "mediatek,mt7988-mmc",
|
|
"mediatek,mt7986-mmc";
|
|
reg = <0 0x11230000 0 0x1000>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&infracfg CLK_INFRA_MSDC400>,
|
|
<&infracfg CLK_INFRA_MSDC2_HCK>,
|
|
<&infracfg CLK_INFRA_133M_MSDC_0_HCK>,
|
|
<&infracfg CLK_INFRA_66M_MSDC_0_HCK>;
|
|
clock-names = "source", "hclk", "source_cg", "axi_cg";
|
|
status = "disabled";
|
|
};
|
|
|
|
ethdma: syscon@15000000 {
|
|
compatible = "mediatek,mt7988-ethdma", "syscon";
|
|
reg = <0 0x15000000 0 0x20000>;
|
|
clock-parent = <&topckgen>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
ethwarp: syscon@15031000 {
|
|
compatible = "mediatek,mt7988-ethwarp", "syscon";
|
|
reg = <0 0x15031000 0 0x1000>;
|
|
clock-parent = <&topckgen>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
eth0: ethernet@15110100 {
|
|
compatible = "mediatek,mt7988-eth", "syscon";
|
|
reg = <0 0x15100000 0 0x20000>;
|
|
mediatek,gmac-id = <0>;
|
|
mediatek,ethsys = <ðdma>;
|
|
mediatek,usxgmiisys = <&usxgmiisys0>;
|
|
mediatek,xfi_pextp = <&xfi_pextp0>;
|
|
mediatek,xfi_pll = <&xfi_pll>;
|
|
mediatek,infracfg = <&topmisc>;
|
|
mediatek,toprgu = <&watchdog>;
|
|
resets = <ðdma ETHDMA_FE_RST>, <ðwarp ETHWARP_GSW_RST>;
|
|
reset-names = "fe", "mcm";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
mediatek,mcm;
|
|
status = "disabled";
|
|
};
|
|
|
|
eth1: ethernet@15110200 {
|
|
compatible = "mediatek,mt7988-eth", "syscon";
|
|
reg = <0 0x15100000 0 0x20000>;
|
|
mediatek,gmac-id = <1>;
|
|
mediatek,ethsys = <ðdma>;
|
|
mediatek,sgmiisys = <&sgmiisys1>;
|
|
mediatek,usxgmiisys = <&usxgmiisys1>;
|
|
mediatek,xfi_pextp = <&xfi_pextp1>;
|
|
mediatek,xfi_pll = <&xfi_pll>;
|
|
mediatek,infracfg = <&topmisc>;
|
|
mediatek,toprgu = <&watchdog>;
|
|
resets = <ðdma ETHDMA_FE_RST>;
|
|
reset-names = "fe";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
mediatek,mcm;
|
|
status = "disabled";
|
|
};
|
|
|
|
eth2: ethernet@15110300 {
|
|
compatible = "mediatek,mt7988-eth", "syscon";
|
|
reg = <0 0x15100000 0 0x20000>;
|
|
mediatek,gmac-id = <2>;
|
|
mediatek,ethsys = <ðdma>;
|
|
mediatek,sgmiisys = <&sgmiisys0>;
|
|
mediatek,usxgmiisys = <&usxgmiisys0>;
|
|
mediatek,xfi_pextp = <&xfi_pextp0>;
|
|
mediatek,xfi_pll = <&xfi_pll>;
|
|
mediatek,infracfg = <&topmisc>;
|
|
mediatek,toprgu = <&watchdog>;
|
|
resets = <ðdma ETHDMA_FE_RST>;
|
|
reset-names = "fe";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
mediatek,mcm;
|
|
status = "disabled";
|
|
};
|
|
};
|