mirror of
https://github.com/smaeul/u-boot.git
synced 2025-09-12 04:56:02 +01:00
1872b7007d
When the CCU binding and driver for the PRCM were written, it seems the intention was to convert the A31 and A23/A33 devicetrees to use them. However, that never happened, so those SoCs still use the old binding, with an MFD for the PRCM, and separate DT nodes for clocks and resets. The specifier in the legacy clock/reset bindings is the register bit offset, so the drivers are trivial. Only the outer PRCM node has a reg property, so the clock/reset drivers use the parent device's MMIO base. Commit-notes: I didn't reuse the sunxi gate/reset ops, because the driver is actually smaller without them. I tested this driver on an A33 tablet. END Series-to: Andre Przywara <andre.przywara@arm.com> Series-to: Jagan Teki <jagan@amarulasolutions.com> Series-to: Lukasz Majewski <lukma@denx.de> Series-to: Sean Anderson <seanga2@gmail.com> Signed-off-by: Samuel Holland <samuel@sholland.org>
28 lines
896 B
Makefile
28 lines
896 B
Makefile
#
|
|
# Copyright (C) 2018 Amarula Solutions.
|
|
#
|
|
# SPDX-License-Identifier: GPL-2.0+
|
|
#
|
|
|
|
obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o
|
|
|
|
obj-$(CONFIG_CLK_SUNXI) += clk_sun6i_rtc.o
|
|
|
|
obj-$(CONFIG_CLK_SUNIV_F1C100S) += clk_f1c100s.o
|
|
obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
|
|
obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
|
|
obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
|
|
obj-$(CONFIG_CLK_SUN6I_A31_R) += clk_a31_r.o
|
|
obj-$(CONFIG_CLK_SUN6I_PRCM) += clk_sun6i_prcm.o
|
|
obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
|
|
obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
|
|
obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
|
|
obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
|
|
obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
|
|
obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
|
|
obj-$(CONFIG_CLK_SUN20I_D1) += clk_d1.o
|
|
obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
|
|
obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
|
|
obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
|
|
obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
|