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1872b7007d
When the CCU binding and driver for the PRCM were written, it seems the intention was to convert the A31 and A23/A33 devicetrees to use them. However, that never happened, so those SoCs still use the old binding, with an MFD for the PRCM, and separate DT nodes for clocks and resets. The specifier in the legacy clock/reset bindings is the register bit offset, so the drivers are trivial. Only the outer PRCM node has a reg property, so the clock/reset drivers use the parent device's MMIO base. Commit-notes: I didn't reuse the sunxi gate/reset ops, because the driver is actually smaller without them. I tested this driver on an A33 tablet. END Series-to: Andre Przywara <andre.przywara@arm.com> Series-to: Jagan Teki <jagan@amarulasolutions.com> Series-to: Lukasz Majewski <lukma@denx.de> Series-to: Sean Anderson <seanga2@gmail.com> Signed-off-by: Samuel Holland <samuel@sholland.org>
105 lines
2.4 KiB
C
105 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
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*/
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#include <clk-uclass.h>
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#include <dm.h>
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#include <reset-uclass.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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struct sun6i_prcm_plat {
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void *base;
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};
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static int sun6i_prcm_set_field(struct udevice *dev, uint reg,
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u32 mask, bool set)
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{
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struct sun6i_prcm_plat *plat = dev_get_plat(dev->parent);
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clrsetbits_le32(plat->base + reg, mask, set ? mask : 0);
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return 0;
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}
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static int sun6i_prcm_clk_enable(struct clk *clk)
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{
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return sun6i_prcm_set_field(clk->dev, 0x28, BIT(clk->id), true);
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}
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static int sun6i_prcm_clk_disable(struct clk *clk)
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{
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return sun6i_prcm_set_field(clk->dev, 0x28, BIT(clk->id), false);
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}
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static const struct clk_ops sun6i_prcm_clk_ops = {
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.enable = sun6i_prcm_clk_enable,
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.disable = sun6i_prcm_clk_disable,
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};
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static const struct udevice_id sun6i_prcm_clk_ids[] = {
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{ .compatible = "allwinner,sun6i-a31-apb0-gates-clk" },
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{ .compatible = "allwinner,sun8i-a23-apb0-gates-clk" },
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{ }
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};
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U_BOOT_DRIVER(sun6i_prcm_clk) = {
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.name = "sun6i_prcm_clk",
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.id = UCLASS_CLK,
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.of_match = sun6i_prcm_clk_ids,
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.ops = &sun6i_prcm_clk_ops,
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};
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static int sun6i_prcm_reset_assert(struct reset_ctl *reset)
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{
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return sun6i_prcm_set_field(reset->dev, 0xb0, BIT(reset->id), false);
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}
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static int sun6i_prcm_reset_deassert(struct reset_ctl *reset)
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{
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return sun6i_prcm_set_field(reset->dev, 0xb0, BIT(reset->id), true);
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}
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static const struct reset_ops sun6i_prcm_reset_ops = {
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.rst_assert = sun6i_prcm_reset_assert,
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.rst_deassert = sun6i_prcm_reset_deassert,
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};
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static const struct udevice_id sun6i_prcm_reset_ids[] = {
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{ .compatible = "allwinner,sun6i-a31-clock-reset" },
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{ }
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};
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U_BOOT_DRIVER(sun6i_prcm_reset) = {
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.name = "sun6i_prcm_reset",
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.id = UCLASS_RESET,
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.of_match = sun6i_prcm_reset_ids,
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.ops = &sun6i_prcm_reset_ops,
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};
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static int sun6i_prcm_of_to_plat(struct udevice *dev)
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{
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struct sun6i_prcm_plat *plat = dev_get_plat(dev);
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plat->base = dev_read_addr_ptr(dev);
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if (!plat->base)
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return -ENOMEM;
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return 0;
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}
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static const struct udevice_id sun6i_prcm_mfd_ids[] = {
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{ .compatible = "allwinner,sun6i-a31-prcm" },
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{ .compatible = "allwinner,sun8i-a23-prcm" },
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{ }
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};
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U_BOOT_DRIVER(sun6i_prcm_mfd) = {
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.name = "sun6i_prcm_mfd",
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.id = UCLASS_SIMPLE_BUS,
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.of_match = sun6i_prcm_mfd_ids,
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.of_to_plat = sun6i_prcm_of_to_plat,
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.plat_auto = sizeof(struct sun6i_prcm_plat),
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};
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