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49249e137d
Boot methods supported: NOR Flash, SPI Flash and SDCARD This patch adds the following basic interfaces: DDR3, eTSEC, DUART, I2C, SD/MMC, USB, SATA, PCIe, NOR Flash, SPI Flash. P1010RDB Overview ----------------- 1Gbyte DDR3 (on board DDR) Local Bus (IFC): 32Mbyte 16bit NOR flash 32Mbyte SLC NAND Flash 64KB CPLD device(GPCM interface) SPI Flash: 128 Mbit SPI Flash memory SD/MMC: connector to interface with the SD memory card SATA: 1 internal SATA connect to 2.5. 160G SATA2 HDD 1 eSATA connector to rear panel USB 2.0: x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface. x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet eTSEC: eTSEC1: Connected to RGMII PHY VSC8641XKO eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY VSC8221 eCAN: Two DB-9 female connectors for Field bus interface UART: supports two UARTs up to 115200 bps for console TDM: 2 FXS ports connected via an external SLIC to the TDM interface. SLIC: SPI SLIC I2C: Serial EEprom Real time clock 256 Kbit M24256 I2C EEPROM PCIe: PCIe and mPCIe connectors. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
99 lines
3.1 KiB
C
99 lines
3.1 KiB
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/mmu.h>
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struct fsl_e_tlb_entry tlb_table[] = {
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/* TLB 0 - for temp stack in cache */
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
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CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
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CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
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CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 0, BOOKE_PAGESZ_4K, 0),
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/* TLB 1 */
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/* *I*** - Covers boot page */
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SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_4K, 1),
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/* *I*G* - CCSRBAR */
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SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 1, BOOKE_PAGESZ_1M, 1),
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#ifndef CONFIG_NAND_SPL
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#ifndef CONFIG_SDCARD
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SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
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0, 2, BOOKE_PAGESZ_16M, 1),
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SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
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CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
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MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
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0, 3, BOOKE_PAGESZ_16M, 1),
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#endif
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#ifdef CONFIG_PCI
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/* *I*G* - PCI */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 4, BOOKE_PAGESZ_1G, 1),
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/* *I*G* - PCI I/O */
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SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 5, BOOKE_PAGESZ_256K, 1),
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#endif
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#endif
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#ifndef CONFIG_SDCARD
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/* *I*G - Board CPLD */
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SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
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MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 6, BOOKE_PAGESZ_256K, 1),
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SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 7, BOOKE_PAGESZ_1M, 1),
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#endif
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#if defined(CONFIG_SYS_RAMBOOT)
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SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
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MAS3_SX|MAS3_SW|MAS3_SR, 0,
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0, 8, BOOKE_PAGESZ_1G, 1)
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#endif
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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