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smaeul-u-boot/arch/riscv/include/asm/arch-andes
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Leo Yu-Chi Liang 61d5c543f3 andes: cpu: Enable cache and TLB ECC support 
Andes CPU supports cache and TLB ECC.
Enable them by default.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-12-27 17:29:07 +08:00
..
csr.h
andes: cpu: Enable cache and TLB ECC support
2023-12-27 17:29:07 +08:00