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smaeul-u-boot/drivers/clk/altera
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Dinesh Maniyam 9d8f814beb clk: altera: n5x: Fix MEMCLKMGR_EXTCNTRST_C0CNTRST to bit(0) 
MEMCLKMGR_EXTCNTRST_C0CNTRST register defined as BIT[0] in documentation
but it is wrongly defined as BIT[7] in u-boot code. This register is used
to hold associated pingpong counter in reset
while PLL and 5:1 mux configuration is changed.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2024-01-22 16:51:17 +08:00
..
clk-agilex.c
common: Drop asm/global_data.h from common header
2021-02-02 15:33:42 -05:00
clk-agilex.h
common: Drop linux/bitops.h from common header
2020-05-18 21:19:23 -04:00
clk-arria10.c
common: Drop asm/global_data.h from common header
2021-02-02 15:33:42 -05:00
clk-mem-n5x.c
drivers: clk: Update license for Intel N5X device
2022-07-01 15:00:39 +08:00
clk-mem-n5x.h
clk: altera: n5x: Fix MEMCLKMGR_EXTCNTRST_C0CNTRST to bit(0)
2024-01-22 16:51:17 +08:00
clk-n5x.c
drivers: clk: Update license for Intel N5X device
2022-07-01 15:00:39 +08:00
clk-n5x.h
drivers: clk: Update license for Intel N5X device
2022-07-01 15:00:39 +08:00
Makefile
drivers: clk: Add memory clock driver for Intel N5X device
2021-08-25 12:55:13 +08:00