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smaeul-u-boot/arch/riscv/cpu
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Leo Yu-Chi Liang 61d5c543f3 andes: cpu: Enable cache and TLB ECC support 
Andes CPU supports cache and TLB ECC.
Enable them by default.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
2023-12-27 17:29:07 +08:00
..
andesv5
andes: cpu: Enable cache and TLB ECC support
2023-12-27 17:29:07 +08:00
fu540
riscv: Remove common.h usage
2023-10-24 16:34:45 -04:00
fu740
riscv: Remove common.h usage
2023-10-24 16:34:45 -04:00
generic
riscv: Remove common.h usage
2023-10-24 16:34:45 -04:00
jh7110
riscv: Remove common.h usage
2023-10-24 16:34:45 -04:00
cpu.c
riscv: Add a reset_cpu() function
2023-12-21 16:07:52 -05:00
Makefile
riscv: Move trap handler codes to mtrap.S
2018-12-18 09:56:27 +08:00
mtrap.S
riscv: Align the trap handler to 64 bytes
2023-11-02 15:15:46 +08:00
start.S
riscv: Remove common.h usage
2023-10-24 16:34:45 -04:00
u-boot-spl.lds
riscv: Update alignment for some sections in linker scripts
2023-04-20 20:45:08 +08:00
u-boot.lds
riscv: Fix alignment of RELA sections in the linker scripts
2023-06-27 10:09:51 +08:00