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28
dts/sun20i-common-regulators.dtsi
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28
dts/sun20i-common-regulators.dtsi
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@ -0,0 +1,28 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
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/ {
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reg_vcc: vcc {
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compatible = "regulator-fixed";
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regulator-name = "vcc";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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reg_vcc_3v3: vcc-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "vcc-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <®_vcc>;
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};
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};
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&pio {
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vcc-pb-supply = <®_vcc_3v3>;
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vcc-pc-supply = <®_vcc_3v3>;
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vcc-pd-supply = <®_vcc_3v3>;
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vcc-pe-supply = <®_vcc_3v3>;
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vcc-pf-supply = <®_vcc_3v3>;
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vcc-pg-supply = <®_vcc_3v3>;
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};
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142
dts/sun20i-d1-mangopi-mq-pro.dts
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142
dts/sun20i-d1-mangopi-mq-pro.dts
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/dts-v1/;
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#include "sun20i-d1.dtsi"
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#include "sun20i-common-regulators.dtsi"
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/ {
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model = "MangoPi MQ Pro";
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compatible = "widora,mangopi-mq-pro", "allwinner,sun20i-d1";
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aliases {
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ethernet0 = &rtl8723ds;
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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leds {
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compatible = "gpio-leds";
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led-0 {
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color = <LED_COLOR_ID_BLUE>;
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function = LED_FUNCTION_STATUS;
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gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */
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};
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};
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reg_avdd2v8: avdd2v8 {
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compatible = "regulator-fixed";
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regulator-name = "avdd2v8";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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vin-supply = <®_vcc_3v3>;
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};
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reg_dvdd: dvdd {
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compatible = "regulator-fixed";
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regulator-name = "dvdd";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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vin-supply = <®_vcc_3v3>;
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};
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reg_vdd_cpu: vdd-cpu {
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compatible = "regulator-fixed";
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regulator-name = "vdd-cpu";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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vin-supply = <®_vcc>;
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};
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wifi_pwrseq: wifi-pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&pio 6 17 GPIO_ACTIVE_LOW>; /* PG17 */
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};
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};
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&cpu0 {
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cpu-supply = <®_vdd_cpu>;
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};
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&dcxo {
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clock-frequency = <24000000>;
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};
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&ehci1 {
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status = "okay";
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};
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&mmc0 {
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bus-width = <4>;
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cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
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disable-wp;
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vmmc-supply = <®_vcc_3v3>;
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vqmmc-supply = <®_vcc_3v3>;
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pinctrl-0 = <&mmc0_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&mmc1 {
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bus-width = <4>;
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mmc-pwrseq = <&wifi_pwrseq>;
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non-removable;
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vmmc-supply = <®_vcc_3v3>;
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vqmmc-supply = <®_vcc_3v3>;
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pinctrl-0 = <&mmc1_pins>;
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pinctrl-names = "default";
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status = "okay";
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rtl8723ds: wifi@1 {
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reg = <1>;
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interrupt-parent = <&pio>;
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interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
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interrupt-names = "host-wake";
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};
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};
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&ohci1 {
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status = "okay";
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};
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&pio {
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vcc-pe-supply = <®_avdd2v8>;
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};
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&uart0 {
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pinctrl-0 = <&uart0_pb8_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&uart1 {
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uart-has-rtscts;
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pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
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pinctrl-names = "default";
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status = "okay";
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bluetooth {
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compatible = "realtek,rtl8723ds-bt";
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device-wake-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
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enable-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */
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host-wake-gpios = <&pio 6 14 GPIO_ACTIVE_HIGH>; /* PG14 */
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};
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};
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&usb_otg {
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dr_mode = "peripheral";
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status = "okay";
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};
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&usbphy {
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usb1_vbus-supply = <®_vcc>;
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status = "okay";
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};
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66
dts/sun20i-d1.dtsi
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66
dts/sun20i-d1.dtsi
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@ -0,0 +1,66 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
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#include "sun20i-d1s.dtsi"
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#include "sunxi-d1-t113.dtsi"
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/ {
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soc {
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lradc: keys@2009800 {
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compatible = "allwinner,sun20i-d1-lradc",
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"allwinner,sun50i-r329-lradc";
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reg = <0x2009800 0x400>;
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interrupts = <SOC_PERIPHERAL_IRQ(61) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_LRADC>;
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resets = <&ccu RST_BUS_LRADC>;
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status = "disabled";
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};
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i2s0: i2s@2032000 {
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compatible = "allwinner,sun20i-d1-i2s",
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"allwinner,sun50i-r329-i2s";
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reg = <0x2032000 0x1000>;
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interrupts = <SOC_PERIPHERAL_IRQ(26) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_I2S0>,
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<&ccu CLK_I2S0>;
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clock-names = "apb", "mod";
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resets = <&ccu RST_BUS_I2S0>;
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dmas = <&dma 3>, <&dma 3>;
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dma-names = "rx", "tx";
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status = "disabled";
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#sound-dai-cells = <0>;
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};
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};
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};
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&pio {
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/omit-if-no-ref/
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dmic_pb11_d0_pin: dmic-pb11-d0-pin {
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pins = "PB11";
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function = "dmic";
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};
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/omit-if-no-ref/
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dmic_pe17_clk_pin: dmic-pe17-clk-pin {
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pins = "PE17";
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function = "dmic";
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};
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/omit-if-no-ref/
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i2c0_pb10_pins: i2c0-pb10-pins {
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pins = "PB10", "PB11";
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function = "i2c0";
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};
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/omit-if-no-ref/
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i2c2_pb0_pins: i2c2-pb0-pins {
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pins = "PB0", "PB1";
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function = "i2c2";
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};
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/omit-if-no-ref/
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uart0_pb8_pins: uart0-pb8-pins {
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pins = "PB8", "PB9";
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function = "uart0";
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};
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};
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117
dts/sun20i-d1s.dtsi
Normal file
117
dts/sun20i-d1s.dtsi
Normal file
@ -0,0 +1,117 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
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#define SOC_PERIPHERAL_IRQ(nr) (nr + 16)
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#include "sunxi-d1s-t113.dtsi"
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/ {
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cpus {
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timebase-frequency = <24000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "thead,c906", "riscv";
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device_type = "cpu";
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reg = <0>;
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clocks = <&ccu CLK_RISCV>;
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d-cache-block-size = <64>;
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d-cache-sets = <256>;
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d-cache-size = <32768>;
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <32768>;
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mmu-type = "riscv,sv39";
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operating-points-v2 = <&opp_table_cpu>;
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riscv,isa = "rv64imafdc";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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"zifencei", "zihpm";
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#cooling-cells = <2>;
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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};
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opp_table_cpu: opp-table-cpu {
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compatible = "operating-points-v2";
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <900000 900000 1100000>;
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};
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opp-1080000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <900000 900000 1100000>;
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};
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};
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soc {
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interrupt-parent = <&plic>;
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riscv_wdt: watchdog@6011000 {
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compatible = "allwinner,sun20i-d1-wdt";
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reg = <0x6011000 0x20>;
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interrupts = <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dcxo>, <&rtc CLK_OSC32K>;
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clock-names = "hosc", "losc";
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};
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plic: interrupt-controller@10000000 {
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compatible = "allwinner,sun20i-d1-plic",
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"thead,c900-plic";
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reg = <0x10000000 0x4000000>;
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interrupts-extended = <&cpu0_intc 11>,
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<&cpu0_intc 9>;
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interrupt-controller;
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riscv,ndev = <175>;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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};
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};
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pmu {
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compatible = "riscv,pmu";
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riscv,event-to-mhpmcounters =
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<0x00003 0x00003 0x00000008>,
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<0x00004 0x00004 0x00000010>,
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<0x00005 0x00005 0x00000200>,
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<0x00006 0x00006 0x00000100>,
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<0x10000 0x10000 0x00004000>,
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<0x10001 0x10001 0x00008000>,
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<0x10002 0x10002 0x00010000>,
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<0x10003 0x10003 0x00020000>,
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<0x10019 0x10019 0x00000040>,
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<0x10021 0x10021 0x00000020>;
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riscv,event-to-mhpmevent =
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<0x00003 0x00000000 0x00000001>,
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<0x00004 0x00000000 0x00000002>,
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<0x00005 0x00000000 0x00000007>,
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<0x00006 0x00000000 0x00000006>,
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<0x10000 0x00000000 0x0000000c>,
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<0x10001 0x00000000 0x0000000d>,
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<0x10002 0x00000000 0x0000000e>,
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<0x10003 0x00000000 0x0000000f>,
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<0x10019 0x00000000 0x00000004>,
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<0x10021 0x00000000 0x00000003>;
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riscv,raw-event-to-mhpmcounters =
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<0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
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<0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
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<0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
|
||||
<0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
|
||||
<0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
|
||||
<0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
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||||
<0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
|
||||
<0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
|
||||
<0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
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<0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
|
||||
<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
|
||||
<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
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||||
};
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||||
};
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15
dts/sunxi-d1-t113.dtsi
Normal file
15
dts/sunxi-d1-t113.dtsi
Normal file
@ -0,0 +1,15 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
|
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|
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/ {
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soc {
|
||||
dsp_wdt: watchdog@1700400 {
|
||||
compatible = "allwinner,sun20i-d1-wdt";
|
||||
reg = <0x1700400 0x20>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(122) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&dcxo>, <&rtc CLK_OSC32K>;
|
||||
clock-names = "hosc", "losc";
|
||||
status = "reserved";
|
||||
};
|
||||
};
|
||||
};
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||||
927
dts/sunxi-d1s-t113.dtsi
Normal file
927
dts/sunxi-d1s-t113.dtsi
Normal file
@ -0,0 +1,927 @@
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||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
|
||||
|
||||
#include <dt-bindings/clock/sun6i-rtc.h>
|
||||
#include <dt-bindings/clock/sun8i-de2.h>
|
||||
#include <dt-bindings/clock/sun8i-tcon-top.h>
|
||||
#include <dt-bindings/clock/sun20i-d1-ccu.h>
|
||||
#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/reset/sun8i-de2.h>
|
||||
#include <dt-bindings/reset/sun20i-d1-ccu.h>
|
||||
#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
dcxo: dcxo-clk {
|
||||
compatible = "fixed-clock";
|
||||
clock-output-names = "dcxo";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
de: display-engine {
|
||||
compatible = "allwinner,sun20i-d1-display-engine";
|
||||
allwinner,pipelines = <&mixer0>, <&mixer1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
dma-noncoherent;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
pio: pinctrl@2000000 {
|
||||
compatible = "allwinner,sun20i-d1-pinctrl";
|
||||
reg = <0x2000000 0x800>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(69) IRQ_TYPE_LEVEL_HIGH>,
|
||||
<SOC_PERIPHERAL_IRQ(71) IRQ_TYPE_LEVEL_HIGH>,
|
||||
<SOC_PERIPHERAL_IRQ(73) IRQ_TYPE_LEVEL_HIGH>,
|
||||
<SOC_PERIPHERAL_IRQ(75) IRQ_TYPE_LEVEL_HIGH>,
|
||||
<SOC_PERIPHERAL_IRQ(77) IRQ_TYPE_LEVEL_HIGH>,
|
||||
<SOC_PERIPHERAL_IRQ(79) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_APB0>,
|
||||
<&dcxo>,
|
||||
<&rtc CLK_OSC32K>;
|
||||
clock-names = "apb", "hosc", "losc";
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#gpio-cells = <3>;
|
||||
#interrupt-cells = <3>;
|
||||
|
||||
/omit-if-no-ref/
|
||||
can0_pins: can0-pins {
|
||||
pins = "PB2", "PB3";
|
||||
function = "can0";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
can1_pins: can1-pins {
|
||||
pins = "PB4", "PB5";
|
||||
function = "can1";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
clk_pg11_pin: clk-pg11-pin {
|
||||
pins = "PG11";
|
||||
function = "clk";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
dsi_4lane_pins: dsi-4lane-pins {
|
||||
pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
|
||||
"PD6", "PD7", "PD8", "PD9";
|
||||
drive-strength = <30>;
|
||||
function = "dsi";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
lcd_rgb666_pins: lcd-rgb666-pins {
|
||||
pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
|
||||
"PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
|
||||
"PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
|
||||
"PD18", "PD19", "PD20", "PD21";
|
||||
function = "lcd0";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
mmc0_pins: mmc0-pins {
|
||||
pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
|
||||
function = "mmc0";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
mmc1_pins: mmc1-pins {
|
||||
pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
|
||||
function = "mmc1";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
mmc2_pins: mmc2-pins {
|
||||
pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
|
||||
function = "mmc2";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
rgmii_pe_pins: rgmii-pe-pins {
|
||||
pins = "PE0", "PE1", "PE2", "PE3", "PE4",
|
||||
"PE5", "PE6", "PE7", "PE8", "PE9",
|
||||
"PE11", "PE12", "PE13", "PE14", "PE15";
|
||||
function = "emac";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
rmii_pe_pins: rmii-pe-pins {
|
||||
pins = "PE0", "PE1", "PE2", "PE3", "PE4",
|
||||
"PE5", "PE6", "PE7", "PE8", "PE9";
|
||||
function = "emac";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
spi0_pins: spi0-pins {
|
||||
pins = "PC2", "PC3", "PC4", "PC5";
|
||||
function = "spi0";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
uart1_pg6_pins: uart1-pg6-pins {
|
||||
pins = "PG6", "PG7";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
|
||||
pins = "PG8", "PG9";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
/omit-if-no-ref/
|
||||
uart3_pb_pins: uart3-pb-pins {
|
||||
pins = "PB6", "PB7";
|
||||
function = "uart3";
|
||||
};
|
||||
};
|
||||
|
||||
ccu: clock-controller@2001000 {
|
||||
compatible = "allwinner,sun20i-d1-ccu";
|
||||
reg = <0x2001000 0x1000>;
|
||||
clocks = <&dcxo>,
|
||||
<&rtc CLK_OSC32K>,
|
||||
<&rtc CLK_IOSC>;
|
||||
clock-names = "hosc", "losc", "iosc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
gpadc: adc@2009000 {
|
||||
compatible = "allwinner,sun20i-d1-gpadc";
|
||||
reg = <0x2009000 0x400>;
|
||||
clocks = <&ccu CLK_BUS_GPADC>;
|
||||
resets = <&ccu RST_BUS_GPADC>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(57) IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
dmic: dmic@2031000 {
|
||||
compatible = "allwinner,sun20i-d1-dmic",
|
||||
"allwinner,sun50i-h6-dmic";
|
||||
reg = <0x2031000 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(24) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_DMIC>,
|
||||
<&ccu CLK_DMIC>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&ccu RST_BUS_DMIC>;
|
||||
dmas = <&dma 8>;
|
||||
dma-names = "rx";
|
||||
status = "disabled";
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
i2s1: i2s@2033000 {
|
||||
compatible = "allwinner,sun20i-d1-i2s",
|
||||
"allwinner,sun50i-r329-i2s";
|
||||
reg = <0x2033000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(27) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_I2S1>,
|
||||
<&ccu CLK_I2S1>;
|
||||
clock-names = "apb", "mod";
|
||||
resets = <&ccu RST_BUS_I2S1>;
|
||||
dmas = <&dma 4>, <&dma 4>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
i2s2: i2s@2034000 {
|
||||
compatible = "allwinner,sun20i-d1-i2s",
|
||||
"allwinner,sun50i-r329-i2s";
|
||||
reg = <0x2034000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_I2S2>,
|
||||
<&ccu CLK_I2S2>;
|
||||
clock-names = "apb", "mod";
|
||||
resets = <&ccu RST_BUS_I2S2>;
|
||||
dmas = <&dma 5>, <&dma 5>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
|
||||
timer: timer@2050000 {
|
||||
compatible = "allwinner,sun20i-d1-timer",
|
||||
"allwinner,sun8i-a23-timer";
|
||||
reg = <0x2050000 0xa0>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(59) IRQ_TYPE_LEVEL_HIGH>,
|
||||
<SOC_PERIPHERAL_IRQ(60) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&dcxo>;
|
||||
};
|
||||
|
||||
wdt: watchdog@20500a0 {
|
||||
compatible = "allwinner,sun20i-d1-wdt-reset",
|
||||
"allwinner,sun20i-d1-wdt";
|
||||
reg = <0x20500a0 0x20>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(63) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&dcxo>, <&rtc CLK_OSC32K>;
|
||||
clock-names = "hosc", "losc";
|
||||
status = "reserved";
|
||||
};
|
||||
|
||||
uart0: serial@2500000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x2500000 0x400>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_UART0>;
|
||||
resets = <&ccu RST_BUS_UART0>;
|
||||
dmas = <&dma 14>, <&dma 14>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@2500400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x2500400 0x400>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_UART1>;
|
||||
resets = <&ccu RST_BUS_UART1>;
|
||||
dmas = <&dma 15>, <&dma 15>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@2500800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x2500800 0x400>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_UART2>;
|
||||
resets = <&ccu RST_BUS_UART2>;
|
||||
dmas = <&dma 16>, <&dma 16>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@2500c00 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x2500c00 0x400>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_UART3>;
|
||||
resets = <&ccu RST_BUS_UART3>;
|
||||
dmas = <&dma 17>, <&dma 17>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@2501000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x2501000 0x400>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_UART4>;
|
||||
resets = <&ccu RST_BUS_UART4>;
|
||||
dmas = <&dma 18>, <&dma 18>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@2501400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x2501400 0x400>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_UART5>;
|
||||
resets = <&ccu RST_BUS_UART5>;
|
||||
dmas = <&dma 19>, <&dma 19>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@2502000 {
|
||||
compatible = "allwinner,sun20i-d1-i2c",
|
||||
"allwinner,sun8i-v536-i2c",
|
||||
"allwinner,sun6i-a31-i2c";
|
||||
reg = <0x2502000 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(9) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_I2C0>;
|
||||
resets = <&ccu RST_BUS_I2C0>;
|
||||
dmas = <&dma 43>, <&dma 43>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@2502400 {
|
||||
compatible = "allwinner,sun20i-d1-i2c",
|
||||
"allwinner,sun8i-v536-i2c",
|
||||
"allwinner,sun6i-a31-i2c";
|
||||
reg = <0x2502400 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_I2C1>;
|
||||
resets = <&ccu RST_BUS_I2C1>;
|
||||
dmas = <&dma 44>, <&dma 44>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c2: i2c@2502800 {
|
||||
compatible = "allwinner,sun20i-d1-i2c",
|
||||
"allwinner,sun8i-v536-i2c",
|
||||
"allwinner,sun6i-a31-i2c";
|
||||
reg = <0x2502800 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(11) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_I2C2>;
|
||||
resets = <&ccu RST_BUS_I2C2>;
|
||||
dmas = <&dma 45>, <&dma 45>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c3: i2c@2502c00 {
|
||||
compatible = "allwinner,sun20i-d1-i2c",
|
||||
"allwinner,sun8i-v536-i2c",
|
||||
"allwinner,sun6i-a31-i2c";
|
||||
reg = <0x2502c00 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(12) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_I2C3>;
|
||||
resets = <&ccu RST_BUS_I2C3>;
|
||||
dmas = <&dma 46>, <&dma 46>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
can0: can@2504000 {
|
||||
compatible = "allwinner,sun20i-d1-can";
|
||||
reg = <0x02504000 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_CAN0>;
|
||||
resets = <&ccu RST_BUS_CAN0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can0_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@2504400 {
|
||||
compatible = "allwinner,sun20i-d1-can";
|
||||
reg = <0x02504400 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_CAN1>;
|
||||
resets = <&ccu RST_BUS_CAN1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can1_pins>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
syscon: syscon@3000000 {
|
||||
compatible = "allwinner,sun20i-d1-system-control";
|
||||
reg = <0x3000000 0x1000>;
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
dma: dma-controller@3002000 {
|
||||
compatible = "allwinner,sun20i-d1-dma";
|
||||
reg = <0x3002000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
|
||||
clock-names = "bus", "mbus";
|
||||
resets = <&ccu RST_BUS_DMA>;
|
||||
dma-channels = <16>;
|
||||
dma-requests = <48>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
sid: efuse@3006000 {
|
||||
compatible = "allwinner,sun20i-d1-sid";
|
||||
reg = <0x3006000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
crypto: crypto@3040000 {
|
||||
compatible = "allwinner,sun20i-d1-crypto";
|
||||
reg = <0x3040000 0x800>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(52) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_CE>,
|
||||
<&ccu CLK_CE>,
|
||||
<&ccu CLK_MBUS_CE>,
|
||||
<&rtc CLK_IOSC>;
|
||||
clock-names = "bus", "mod", "ram", "trng";
|
||||
resets = <&ccu RST_BUS_CE>;
|
||||
};
|
||||
|
||||
mbus: dram-controller@3102000 {
|
||||
compatible = "allwinner,sun20i-d1-mbus";
|
||||
reg = <0x3102000 0x1000>,
|
||||
<0x3103000 0x1000>;
|
||||
reg-names = "mbus", "dram";
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_MBUS>,
|
||||
<&ccu CLK_DRAM>,
|
||||
<&ccu CLK_BUS_DRAM>;
|
||||
clock-names = "mbus", "dram", "bus";
|
||||
dma-ranges = <0 0x40000000 0x80000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
mmc0: mmc@4020000 {
|
||||
compatible = "allwinner,sun20i-d1-mmc";
|
||||
reg = <0x4020000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
|
||||
clock-names = "ahb", "mmc";
|
||||
resets = <&ccu RST_BUS_MMC0>;
|
||||
reset-names = "ahb";
|
||||
cap-sd-highspeed;
|
||||
max-frequency = <150000000>;
|
||||
no-mmc;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mmc1: mmc@4021000 {
|
||||
compatible = "allwinner,sun20i-d1-mmc";
|
||||
reg = <0x4021000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
|
||||
clock-names = "ahb", "mmc";
|
||||
resets = <&ccu RST_BUS_MMC1>;
|
||||
reset-names = "ahb";
|
||||
cap-sd-highspeed;
|
||||
max-frequency = <150000000>;
|
||||
no-mmc;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mmc2: mmc@4022000 {
|
||||
compatible = "allwinner,sun20i-d1-emmc",
|
||||
"allwinner,sun50i-a100-emmc";
|
||||
reg = <0x4022000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
|
||||
clock-names = "ahb", "mmc";
|
||||
resets = <&ccu RST_BUS_MMC2>;
|
||||
reset-names = "ahb";
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <150000000>;
|
||||
mmc-ddr-1_8v;
|
||||
mmc-ddr-3_3v;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi0: spi@4025000 {
|
||||
compatible = "allwinner,sun20i-d1-spi",
|
||||
"allwinner,sun50i-r329-spi";
|
||||
reg = <0x04025000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma 22>, <&dma 22>;
|
||||
dma-names = "rx", "tx";
|
||||
resets = <&ccu RST_BUS_SPI0>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi1: spi@4026000 {
|
||||
compatible = "allwinner,sun20i-d1-spi-dbi",
|
||||
"allwinner,sun50i-r329-spi-dbi",
|
||||
"allwinner,sun50i-r329-spi";
|
||||
reg = <0x04026000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(16) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma 23>, <&dma 23>;
|
||||
dma-names = "rx", "tx";
|
||||
resets = <&ccu RST_BUS_SPI1>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
usb_otg: usb@4100000 {
|
||||
compatible = "allwinner,sun20i-d1-musb",
|
||||
"allwinner,sun8i-a33-musb";
|
||||
reg = <0x4100000 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "mc";
|
||||
clocks = <&ccu CLK_BUS_OTG>;
|
||||
resets = <&ccu RST_BUS_OTG>;
|
||||
extcon = <&usbphy 0>;
|
||||
phys = <&usbphy 0>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy: phy@4100400 {
|
||||
compatible = "allwinner,sun20i-d1-usb-phy";
|
||||
reg = <0x4100400 0x100>,
|
||||
<0x4101800 0x100>,
|
||||
<0x4200800 0x100>;
|
||||
reg-names = "phy_ctrl",
|
||||
"pmu0",
|
||||
"pmu1";
|
||||
clocks = <&dcxo>,
|
||||
<&dcxo>;
|
||||
clock-names = "usb0_phy",
|
||||
"usb1_phy";
|
||||
resets = <&ccu RST_USB_PHY0>,
|
||||
<&ccu RST_USB_PHY1>;
|
||||
reset-names = "usb0_reset",
|
||||
"usb1_reset";
|
||||
status = "disabled";
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
ehci0: usb@4101000 {
|
||||
compatible = "allwinner,sun20i-d1-ehci",
|
||||
"generic-ehci";
|
||||
reg = <0x4101000 0x100>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_OHCI0>,
|
||||
<&ccu CLK_BUS_EHCI0>,
|
||||
<&ccu CLK_USB_OHCI0>;
|
||||
resets = <&ccu RST_BUS_OHCI0>,
|
||||
<&ccu RST_BUS_EHCI0>;
|
||||
phys = <&usbphy 0>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@4101400 {
|
||||
compatible = "allwinner,sun20i-d1-ohci",
|
||||
"generic-ohci";
|
||||
reg = <0x4101400 0x100>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_OHCI0>,
|
||||
<&ccu CLK_USB_OHCI0>;
|
||||
resets = <&ccu RST_BUS_OHCI0>;
|
||||
phys = <&usbphy 0>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci1: usb@4200000 {
|
||||
compatible = "allwinner,sun20i-d1-ehci",
|
||||
"generic-ehci";
|
||||
reg = <0x4200000 0x100>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_OHCI1>,
|
||||
<&ccu CLK_BUS_EHCI1>,
|
||||
<&ccu CLK_USB_OHCI1>;
|
||||
resets = <&ccu RST_BUS_OHCI1>,
|
||||
<&ccu RST_BUS_EHCI1>;
|
||||
phys = <&usbphy 1>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci1: usb@4200400 {
|
||||
compatible = "allwinner,sun20i-d1-ohci",
|
||||
"generic-ohci";
|
||||
reg = <0x4200400 0x100>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_OHCI1>,
|
||||
<&ccu CLK_USB_OHCI1>;
|
||||
resets = <&ccu RST_BUS_OHCI1>;
|
||||
phys = <&usbphy 1>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
emac: ethernet@4500000 {
|
||||
compatible = "allwinner,sun20i-d1-emac",
|
||||
"allwinner,sun50i-a64-emac";
|
||||
reg = <0x4500000 0x10000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
clocks = <&ccu CLK_BUS_EMAC>;
|
||||
clock-names = "stmmaceth";
|
||||
resets = <&ccu RST_BUS_EMAC>;
|
||||
reset-names = "stmmaceth";
|
||||
syscon = <&syscon>;
|
||||
status = "disabled";
|
||||
|
||||
mdio: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
display_clocks: clock-controller@5000000 {
|
||||
compatible = "allwinner,sun20i-d1-de2-clk",
|
||||
"allwinner,sun50i-h5-de2-clk";
|
||||
reg = <0x5000000 0x10000>;
|
||||
clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&ccu RST_BUS_DE>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
mixer0: mixer@5100000 {
|
||||
compatible = "allwinner,sun20i-d1-de2-mixer-0";
|
||||
reg = <0x5100000 0x100000>;
|
||||
clocks = <&display_clocks CLK_BUS_MIXER0>,
|
||||
<&display_clocks CLK_MIXER0>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&display_clocks RST_MIXER0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mixer0_out: port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mixer0_out_tcon_top_mixer0: endpoint {
|
||||
remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mixer1: mixer@5200000 {
|
||||
compatible = "allwinner,sun20i-d1-de2-mixer-1";
|
||||
reg = <0x5200000 0x100000>;
|
||||
clocks = <&display_clocks CLK_BUS_MIXER1>,
|
||||
<&display_clocks CLK_MIXER1>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&display_clocks RST_MIXER1>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mixer1_out: port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mixer1_out_tcon_top_mixer1: endpoint {
|
||||
remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi: dsi@5450000 {
|
||||
compatible = "allwinner,sun20i-d1-mipi-dsi",
|
||||
"allwinner,sun50i-a100-mipi-dsi";
|
||||
reg = <0x5450000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_MIPI_DSI>,
|
||||
<&tcon_top CLK_TCON_TOP_DSI>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&ccu RST_BUS_MIPI_DSI>;
|
||||
phys = <&dphy>;
|
||||
phy-names = "dphy";
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
dsi_in_tcon_lcd0: endpoint {
|
||||
remote-endpoint = <&tcon_lcd0_out_dsi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dphy: phy@5451000 {
|
||||
compatible = "allwinner,sun20i-d1-mipi-dphy",
|
||||
"allwinner,sun50i-a100-mipi-dphy";
|
||||
reg = <0x5451000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_MIPI_DSI>,
|
||||
<&ccu CLK_MIPI_DSI>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&ccu RST_BUS_MIPI_DSI>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
tcon_top: tcon-top@5460000 {
|
||||
compatible = "allwinner,sun20i-d1-tcon-top";
|
||||
reg = <0x5460000 0x1000>;
|
||||
clocks = <&ccu CLK_BUS_DPSS_TOP>,
|
||||
<&ccu CLK_TCON_TV>,
|
||||
<&ccu CLK_TVE>,
|
||||
<&ccu CLK_TCON_LCD0>;
|
||||
clock-names = "bus", "tcon-tv0", "tve0", "dsi";
|
||||
clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
|
||||
resets = <&ccu RST_BUS_DPSS_TOP>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_top_mixer0_in: port@0 {
|
||||
reg = <0>;
|
||||
|
||||
tcon_top_mixer0_in_mixer0: endpoint {
|
||||
remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_top_mixer0_out: port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
|
||||
};
|
||||
|
||||
tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_top_mixer1_in: port@2 {
|
||||
reg = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_top_mixer1_in_mixer1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_top_mixer1_out: port@3 {
|
||||
reg = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
|
||||
};
|
||||
|
||||
tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_top_hdmi_in: port@4 {
|
||||
reg = <4>;
|
||||
|
||||
tcon_top_hdmi_in_tcon_tv0: endpoint {
|
||||
remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_top_hdmi_out: port@5 {
|
||||
reg = <5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tcon_lcd0: lcd-controller@5461000 {
|
||||
compatible = "allwinner,sun20i-d1-tcon-lcd";
|
||||
reg = <0x5461000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(90) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_TCON_LCD0>,
|
||||
<&ccu CLK_TCON_LCD0>;
|
||||
clock-names = "ahb", "tcon-ch0";
|
||||
clock-output-names = "tcon-pixel-clock";
|
||||
resets = <&ccu RST_BUS_TCON_LCD0>,
|
||||
<&ccu RST_BUS_LVDS0>;
|
||||
reset-names = "lcd", "lvds";
|
||||
#clock-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_lcd0_in: port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
|
||||
};
|
||||
|
||||
tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_lcd0_out: port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_lcd0_out_dsi: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&dsi_in_tcon_lcd0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tcon_tv0: lcd-controller@5470000 {
|
||||
compatible = "allwinner,sun20i-d1-tcon-tv";
|
||||
reg = <0x5470000 0x1000>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_TCON_TV>,
|
||||
<&tcon_top CLK_TCON_TOP_TV0>;
|
||||
clock-names = "ahb", "tcon-ch1";
|
||||
resets = <&ccu RST_BUS_TCON_TV>;
|
||||
reset-names = "lcd";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_tv0_in: port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
|
||||
};
|
||||
|
||||
tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon_tv0_out: port@1 {
|
||||
reg = <1>;
|
||||
|
||||
tcon_tv0_out_tcon_top_hdmi: endpoint {
|
||||
remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ppu: power-controller@7001000 {
|
||||
compatible = "allwinner,sun20i-d1-ppu";
|
||||
reg = <0x7001000 0x1000>;
|
||||
clocks = <&r_ccu CLK_BUS_R_PPU>;
|
||||
resets = <&r_ccu RST_BUS_R_PPU>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
r_ccu: clock-controller@7010000 {
|
||||
compatible = "allwinner,sun20i-d1-r-ccu";
|
||||
reg = <0x7010000 0x400>;
|
||||
clocks = <&dcxo>,
|
||||
<&rtc CLK_OSC32K>,
|
||||
<&rtc CLK_IOSC>,
|
||||
<&ccu CLK_PLL_PERIPH0_DIV3>;
|
||||
clock-names = "hosc", "losc", "iosc", "pll-periph";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
rtc: rtc@7090000 {
|
||||
compatible = "allwinner,sun20i-d1-rtc",
|
||||
"allwinner,sun50i-r329-rtc";
|
||||
reg = <0x7090000 0x400>;
|
||||
interrupts = <SOC_PERIPHERAL_IRQ(144) IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&r_ccu CLK_BUS_R_RTC>,
|
||||
<&dcxo>,
|
||||
<&r_ccu CLK_R_AHB>;
|
||||
clock-names = "bus", "hosc", "ahb";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
1374
dts/ubuntu.24.04.devicetree.dts
Normal file
1374
dts/ubuntu.24.04.devicetree.dts
Normal file
File diff suppressed because it is too large
Load Diff
90
ubuntu.24.04.pinctrl.txt
Normal file
90
ubuntu.24.04.pinctrl.txt
Normal file
@ -0,0 +1,90 @@
|
||||
Pinmux settings per pin
|
||||
Format: pin (name): mux_owner|gpio_owner (strict) hog?
|
||||
pin 32 (PB0): device 2502800.i2c function i2c2 group PB0
|
||||
pin 33 (PB1): device 2502800.i2c function i2c2 group PB1
|
||||
pin 34 (PB2): UNCLAIMED
|
||||
pin 35 (PB3): UNCLAIMED
|
||||
pin 36 (PB4): UNCLAIMED
|
||||
pin 37 (PB5): UNCLAIMED
|
||||
pin 38 (PB6): UNCLAIMED
|
||||
pin 39 (PB7): UNCLAIMED
|
||||
pin 40 (PB8): device 2500000.serial function uart0 group PB8
|
||||
pin 41 (PB9): device 2500000.serial function uart0 group PB9
|
||||
pin 42 (PB10): UNCLAIMED
|
||||
pin 43 (PB11): UNCLAIMED
|
||||
pin 44 (PB12): UNCLAIMED
|
||||
pin 64 (PC0): device 2008000.led-controller function ledc group PC0
|
||||
pin 65 (PC1): UNCLAIMED
|
||||
pin 66 (PC2): device 4025000.spi function spi0 group PC2
|
||||
pin 67 (PC3): device 4025000.spi function spi0 group PC3
|
||||
pin 68 (PC4): device 4025000.spi function spi0 group PC4
|
||||
pin 69 (PC5): device 4025000.spi function spi0 group PC5
|
||||
pin 70 (PC6): device 4025000.spi function spi0 group PC6
|
||||
pin 71 (PC7): device 4025000.spi function spi0 group PC7
|
||||
pin 96 (PD0): UNCLAIMED
|
||||
pin 97 (PD1): UNCLAIMED
|
||||
pin 98 (PD2): UNCLAIMED
|
||||
pin 99 (PD3): UNCLAIMED
|
||||
pin 100 (PD4): UNCLAIMED
|
||||
pin 101 (PD5): UNCLAIMED
|
||||
pin 102 (PD6): UNCLAIMED
|
||||
pin 103 (PD7): UNCLAIMED
|
||||
pin 104 (PD8): UNCLAIMED
|
||||
pin 105 (PD9): UNCLAIMED
|
||||
pin 106 (PD10): device 4026000.spi function spi1 group PD10
|
||||
pin 107 (PD11): device 4026000.spi function spi1 group PD11
|
||||
pin 108 (PD12): device 4026000.spi function spi1 group PD12
|
||||
pin 109 (PD13): device 4026000.spi function spi1 group PD13
|
||||
pin 110 (PD14): device 4026000.spi function spi1 group PD14
|
||||
pin 111 (PD15): device 4026000.spi function spi1 group PD15
|
||||
pin 112 (PD16): device 2000c00.pwm function pwm0 group PD16
|
||||
pin 113 (PD17): UNCLAIMED
|
||||
pin 114 (PD18): UNCLAIMED
|
||||
pin 115 (PD19): GPIO 2000000.pinctrl:115
|
||||
pin 116 (PD20): GPIO 2000000.pinctrl:116
|
||||
pin 117 (PD21): GPIO 2000000.pinctrl:117
|
||||
pin 118 (PD22): UNCLAIMED
|
||||
pin 128 (PE0): UNCLAIMED
|
||||
pin 129 (PE1): UNCLAIMED
|
||||
pin 130 (PE2): UNCLAIMED
|
||||
pin 131 (PE3): UNCLAIMED
|
||||
pin 132 (PE4): UNCLAIMED
|
||||
pin 133 (PE5): UNCLAIMED
|
||||
pin 134 (PE6): UNCLAIMED
|
||||
pin 135 (PE7): UNCLAIMED
|
||||
pin 136 (PE8): UNCLAIMED
|
||||
pin 137 (PE9): UNCLAIMED
|
||||
pin 138 (PE10): UNCLAIMED
|
||||
pin 139 (PE11): UNCLAIMED
|
||||
pin 140 (PE12): UNCLAIMED
|
||||
pin 141 (PE13): UNCLAIMED
|
||||
pin 142 (PE14): UNCLAIMED
|
||||
pin 143 (PE15): UNCLAIMED
|
||||
pin 144 (PE16): UNCLAIMED
|
||||
pin 145 (PE17): UNCLAIMED
|
||||
pin 160 (PF0): device 4020000.mmc function mmc0 group PF0
|
||||
pin 161 (PF1): device 4020000.mmc function mmc0 group PF1
|
||||
pin 162 (PF2): device 4020000.mmc function mmc0 group PF2
|
||||
pin 163 (PF3): device 4020000.mmc function mmc0 group PF3
|
||||
pin 164 (PF4): device 4020000.mmc function mmc0 group PF4
|
||||
pin 165 (PF5): device 4020000.mmc function mmc0 group PF5
|
||||
pin 166 (PF6): GPIO 2000000.pinctrl:166
|
||||
pin 192 (PG0): device 4021000.mmc function mmc1 group PG0
|
||||
pin 193 (PG1): device 4021000.mmc function mmc1 group PG1
|
||||
pin 194 (PG2): device 4021000.mmc function mmc1 group PG2
|
||||
pin 195 (PG3): device 4021000.mmc function mmc1 group PG3
|
||||
pin 196 (PG4): device 4021000.mmc function mmc1 group PG4
|
||||
pin 197 (PG5): device 4021000.mmc function mmc1 group PG5
|
||||
pin 198 (PG6): device 2500400.serial function uart1 group PG6
|
||||
pin 199 (PG7): device 2500400.serial function uart1 group PG7
|
||||
pin 200 (PG8): device 2500400.serial function uart1 group PG8
|
||||
pin 201 (PG9): device 2500400.serial function uart1 group PG9
|
||||
pin 202 (PG10): UNCLAIMED
|
||||
pin 203 (PG11): UNCLAIMED
|
||||
pin 204 (PG12): GPIO 2000000.pinctrl:204
|
||||
pin 205 (PG13): UNCLAIMED
|
||||
pin 206 (PG14): UNCLAIMED
|
||||
pin 207 (PG15): UNCLAIMED
|
||||
pin 208 (PG16): UNCLAIMED
|
||||
pin 209 (PG17): UNCLAIMED
|
||||
pin 210 (PG18): UNCLAIMED
|
||||
Loading…
x
Reference in New Issue
Block a user