26008 Commits

Author SHA1 Message Date
Christian Marangi
54f8ba658f clk: mediatek: mt7986: rename CK to CLK
Rename each entry from CK to CLK to match the include in upstream kernel
linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
2024-08-19 16:14:44 -06:00
Christian Marangi
ba7969c5fb clk: mediatek: mt7986: convert to unified infracfg gates + muxes
Convert to infracfg gates + muxes implementation now that it's
supported.

Drop infracfg-ao nodes and rename all infracfg-ao clocks to infracfg.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:44 -06:00
Christian Marangi
efc82b035f clk: mediatek: mt7986: replace infracfg ID with upstream linux
Replace infracfg clk ID with upstream linux version.

The same format is used here with the factor first, then mux and then
gates.

To correctly reference the gates in clk_gate function, define the
gates_offs value in clk_tree now that they are at an offset from mux and
factor.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:44 -06:00
Christian Marangi
6636017ad3 clk: mediatek: mt7986: move INFRA_TRNG_CK to the bottom of the list
Move INFRA_TRNG_CK to the bottom of the list to have a 1:1 match with
upstream linux clock ID.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:44 -06:00
Christian Marangi
e4bdf9b004 clk: mediatek: mt7986: comment out CK_TOP_A_TUNER as not used
Comment out CK_TOP_A_TUNER as not used and not defined in upstream
kernel linux. This is to permit support of OF_UPSTREAM and have a 1:1
match with upstream linux clock ID.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:44 -06:00
Christian Marangi
7124b9928a clk: mediatek: mt7986: drop 1/1 spurious factor for topckgen
Now that we can have advanced parent handling for mux, we can drop
spurious topckgen 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7986.

Drop the factor entry from mt7986-clk.h and reference to them in
mt7981.dtsi. Muxes and gates are updated to reference the apmixed clk
following how it's done in upstream kernel linux. Add relevant clk type
flag in clk_tree for apmixed.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Christian Marangi
8cf99baf99 clk: mediatek: mt7986: reorder TOPCKGEN factor ID
Reorder TOPCKGEN factor ID to put TOP_FACTOR first and then PLL. This is
to match how it's done in upstream kernel linux and in preparation for
OF_UPSTREAM support.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Christian Marangi
1062187a4b clk: mediatek: mt7986: rename TOPCKGEN factor clock to upstream naming
Rename TOPCKGEN factor clock to upstream neaming.
Upstream kernel linux reference the factor clock for apmixedpll with the
"pll" suffix. Align the naming to the upstream naming format in
preparation for OF_UPSTREAM support.

Also rename rtc clock to drop the CB_ as upstream doesn't have that.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Christian Marangi
b87f40fb7e clk: mediatek: mt7986: fix typo for infra_i2c0_ck
Fix a typo for infra_i2c0_ck where 0 was misspelled as O.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Christian Marangi
a6c0761f65 clk: mediatek: mt7986: add missing entry for IPCIE_PIPE_CK infra gate
Add missing entry for IPCIE_PIPE_CK infra gate clock. Renumber the clock
order to match the expected offset in the gate array.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Christian Marangi
6df8029c9e clk: mediatek: mt7986: drop 1/1 infracfg spurious factor
Now that we can have advanced parent handling for mux, we can drop
spurious infracfg 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7986.

Drop the factor entry from mt7986-clk.h and reference to them in
mt7981.dtsi. Muxes and gates are updated to reference the topckgen clk
following how it's done in upstream kernel linux. Add relevant clk type
flag in clk_tree for infracfg and topckgen.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Christian Marangi
6267725ccc clk: mediatek: mt7986: fix wrong parent for INFRA_ADC_26M_CK
Fix wrong parent for INFRA_ADC_26M_CK as should be INFRA_ADC_FRC_CK
instead of INFRA_CK_F26M. This is to match implementation on upstream
kernel linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Christian Marangi
5e4ee4b354 clk: mediatek: mt7986: rename 66M_MCK to SYSAXI_D2
Upstream kernel linux clock include use SYSAXI_D2 instead of 66M_MCK.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Christian Marangi
e69a1fed16 clk: mediatek: mt7986: rename CB_CKSQ_40M to TOP_XTAL
Upstream kernel linux clock include use TOP_XTAL instead of CB_CKSQ_40M.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Christian Marangi
5dd509788d clk: mediatek: mt7986: fix wrong shift for PCIe clocks
Fix wrong shift for PCIe clocks. This cause the PCIe port to malfunction
as the gate clocks weren't correctly enabled.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:43 -06:00
Tom Rini
2f71d6ef32 Merge patch series "clk: mediatek: mt7988: clk migration for OF_UPSTREAM"
Christian Marangi <ansuelsmth@gmail.com> says:

These are all the required patches to migrate clk and correctly support
OF_UPSTREAM. This will align the clk index to upstream to support the same
clk implementation with downstream and upstream DTS.
2024-08-19 16:14:29 -06:00
Christian Marangi
99c5fa184b clk: mediatek: mt7988: rename CK to CLK
Rename each entry from CK to CLK to match the include in upstream kernel
linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
2024-08-19 16:14:09 -06:00
Christian Marangi
ef4a648587 clk: mediatek: mt7988: convert to unified infracfg gates + muxes
Convert to infracfg gates + muxes implementation now that it's
supported.

Drop infracfg-ao nodes and rename all infracfg-ao clocks to infracfg.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
4f100a0c70 clk: mediatek: mt7988: replace clock ID with upstream linux
Replace infracfg clk ID with upstream linux version.

The same format is used here with the factor first, then mux and then
gates.

To correctly reference the gates in clk_gate function, define the
gates_offs value in clk_tree now that they are at an offset from mux and
factor.

Drop any comment that reference the clock ID as we now have a 1:1 match
with upstream kernel linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
6e54f037df clk: mediatek: mt7988: comment out infracfg clk not defined
Comment out infracfg clk not defined in upstream kernel linux clock ID
include. These clock are not used and can be safely commented. Keep them
just to have a reference of their existence.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
d061f73a92 clk: mediatek: mt7988: drop 1/1 spurious factor for topckgen
Now that we can have advanced parent handling for mux, we can drop
spurious topckgen 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7988.

Drop the factor entry from mt7988-clk.h and reference to them in
mt7988.dtsi. Muxes and gates are updated to reference the apmixed clk
following how it's done in upstream kernel linux. Add relevant clk type
flag in clk_tree for apmixed and topckgen.

Also move TOP_XTAL to the fixed clock table following how it's done in
upstream linux kernel.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
1bafda9851 clk: mediatek: mt7988: reorder TOPCKGEN factor ID
Reorder TOPCKGEN factor ID to put TOP_FACTOR first and then PLL. This is
to match how it's done in upstream kernel linux and in preparation for
OF_UPSTREAM support.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
8b75c2c479 clk: mediatek: mt7988: rename TOPCKGEN factor clock to upstream naming
Rename TOPCKGEN factor clock to upstream neaming.
Upstream kernel linux reference the factor clock for apmixedpll with the
"pll" suffix. Align the naming to the upstream naming format in
preparation for OF_UPSTREAM support.

Also rename rtc clock to drop the CB_ as upstream doesn't have that.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
78507c3a9f clk: mediatek: mt7988: drop 1/1 infracfg spurious factor
Now that we can have advanced parent handling for mux, we can drop
spurious infracfg 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7988.

Drop the factor entry from mt7988-clk.h and reference to them in
mt7988.dtsi. Muxes and gates are updated to reference the topckgen clk
following how it's done in upstream kernel linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
caa5f27382 clk: mediatek: mt7988: fix wrong parent for INFRA_PCIE_PERI_26M_CK_P2
Fix wrong parent for INFRA_PCIE_PERI_26M_CK_P2 as should be
INFRA_PCIE_PERI_26M_CK_P3 instead of INFRA_F26M_O0. This is to match
implementation on upstream kernel linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
49d11169f7 clk: mediatek: mt7988: move INFRA_PCIE_PERI_26M_CK_Px clock at top
Move INFRA_PCIE_PERI_26M_CK_Px clock at top of the infracfg gates
in preparation for support of OF_UPSTREAM to have a 1:1 match with
upstream clock ID.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
603585892f clk: mediatek: mt7988: rename TOP_CK_NPU_SEL_CM_TOPS_SEL to TOP_NPU_SEL
Upstream kernel linux clock include use TOP_NPU_SEL instead of
TOP_CK_NPU_SEL_CM_TOPS_SEL.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
e7ecdd5a46 clk: mediatek: mt7988: rename TOP_DA_SELM_XTAL_SEL to TOP_DA_SEL
Upstream kernel linux clock include use TOP_DA_SEL instead of
TOP_DA_SELM_XTAL_SEL.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Christian Marangi
b76b75bfc6 clk: mediatek: mt7988: rename CB_CKSQ_40M to TOP_XTAL
Upstream kernel linux clock include use TOP_XTAL instead of CB_CKSQ_40M.
Rename this clock to the upstream kernel in preparation for support of
OF_UPSTREAM.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:14:09 -06:00
Tom Rini
98cccbd680 Merge patch series "clk: mediatek: mt7981: clk migration for OF_UPSTREAM"
Christian Marangi <ansuelsmth@gmail.com> says:

These are all the required patches to migrate clk and correctly support
OF_UPSTREAM. This will align the clk index to upstream to support the same
clk implementation with downstream and upstream DTS.
2024-08-19 16:13:57 -06:00
Christian Marangi
02de3b9f04 clk: mediatek: mt7981: rename CK to CLK
Rename each entry from CK to CLK to match the include in upstream kernel
linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:13:13 -06:00
Christian Marangi
99da5bbd80 clk: mediatek: mt7981: convert to unified infracfg gates + muxes
Convert to infracfg gates + muxes implementation now that it's
supported.

Drop infracfg-ao nodes and rename all infracfg-ao clocks to infracfg.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:13:13 -06:00
Christian Marangi
2d20cc4064 clk: mediatek: mt7981: fix support for pwm3 clock
Add and fix support for pwm3 clock. In the pwm DTSI node we were
actually using PWM2 clock for PWM3. Now that we have correct ID also add
the missing entry of gate and mux to support PWM3 clock.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:13:13 -06:00
Christian Marangi
2967f21182 clk: mediatek: mt7981: replace infracfg ID with upstream linux
Replace infracfg clk ID with upstream linux version.

Add some missing clk for PWM3 and for PCIe. The same format is used here
with the factor first, then mux and then gates.

To correctly reference the gates in clk_gate function, define the
gates_offs value in clk_tree now that they are at an offset from mux and
factor.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:13:13 -06:00
Christian Marangi
78487cd093 clk: mediatek: mt7981: drop 1/1 spurious factor
Now that we can have advanced parent handling for mux, we can drop
spurious infracfg 1/1 factor. This is in preparation to make the clk
ID match the ID in upstream include for mt7981.

Drop the factor entry from mt7981-clk.h and reference to them in
mt7981.dtsi. Muxes and gates are updated to reference the topckgen clk
following how it's done in upstream kernel linux. Add relevant clk type
flag in clk_tree for infracfg and topckgen.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:13:13 -06:00
Christian Marangi
807624c1e1 clk: mediatek: mt7981: implement sgmii0/1 clock
Implement missing sgmii0/1 clock and update the compatible the DTS to
match upstream kernel linux and in preparation for OF_UPSTREAM support
since the ethernet node define these additional clocks.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:13:13 -06:00
Christian Marangi
e568997faa clk: mediatek: mt7981: fix wrong parent list for INFRA_PWM1_SEL mux
Fix wrong parent list for INFRA_PWM1_SEL mux. The list is incorrect and
the parents are just 2. This also match the upstream linux
implementation.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:13:13 -06:00
Christian Marangi
02af9cad70 clk: mediatek: mt7981: fix wrong parent for TOP_FAUD clock
Fix wrong parent for TOP_FAUD clock. Upstream linux sets the parent for
TOP_FAUD to TOP_AUD_SEL instead of CB_CKSQ_40M.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:13:13 -06:00
Christian Marangi
a3cc4a4810 clk: mediatek: mt7981: fix wrong mux width for pwm2 and pwm1 clock
Fix wrong mux width for pwm2 and pwm1. Upstream have width 1 but U-Boot
have width set to 2. Change the value to follow upstream implementation.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:13:13 -06:00
Christian Marangi
99d3da81bd clk: mediatek: mt7981: fix typo for infra_i2c0_ck
Fix a typo for infra_i2c0_ck where 0 was misspelled as O.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:13:13 -06:00
Christian Marangi
7c732d09f9 clk: mediatek: mt7981: add missing clock for infra_ipcie_pipe
Add missing clock for infra_ipcie_pipe to make PCIe correctly work. This
clock is a parent of the fixed clock from topckgen cb_cksq_40m.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:13:13 -06:00
Tom Rini
f5703ceeb9 Merge patch series "clk: mediatek: mt7623: clk migration for OF_UPSTREAM"
Christian Marangi <ansuelsmth@gmail.com> says:

These are all the required patches to migrate clk and correctly support
OF_UPSTREAM. This will align the clk index to upstream to support the same
clk implementation with downstream and upstream DTS.
2024-08-19 16:13:01 -06:00
Christian Marangi
5c15548f7d clk: mediatek: mt7623: remap peri clock ID and add MUX
Upstream kernel linux makes use of peri clock MUX to setup UART.

Add definition for these and add remap table as in the upstream clock ID
order gates are before MUX but we require MUX first and then clocks in
our downstream driver.

Convert the peri clk tree to MUX + GATE implementation.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
2024-08-19 16:12:51 -06:00
Christian Marangi
57f7ddd1b2 clk: mediatek: mt7623: remap apmixedsys clock ID
Define remap table also for apmixedsys clock ID. The clock ID starts
from 1 instead of 0 in upstream kernel linux.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:12:51 -06:00
Christian Marangi
108a62b57e clk: mediatek: mt7623: define id_offs_map and import clk ID from upstream
Define id_offs_map and use clk ID form upstream linux kernel to have a
1:1 match for the TOPCKGEN clock and permit usage of OF_UPSTREAM with
upstream dtsi.

For all the gate clock, the clk ID starts from 1 instead of zero. Define
an additional clock tree for them and set the .gates_offs to 1 to
account for this.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:12:51 -06:00
Christian Marangi
efd35fa07b clk: mediatek: mt7623: split clk tree to dedicated topckgen and apmixed
Split clk tree to dedicated topckgen and apmixed in preparation for
remap table.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:12:51 -06:00
Christian Marangi
c721d5a92a clk: mediatek: mt7623: fix broken peri_cgs clk with XTAL parents
Fix broken peri_cgs and infra_cgs clock with XTAL parents as they have
wrong definition of the parent type.

Correctly fix them and use CLK_PARENT_XTAL for them.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-08-19 16:12:51 -06:00
Sam Protsenko
9bedead15a mmc: exynos_dw_mmc: Improve coding style
Fix most of checkpatch warnings and other obvious style issues.

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-08-19 16:09:06 +09:00
Sam Protsenko
549afd7f32 mmc: exynos_dw_mmc: Use dev->name as driver's displayed name
Reduce U-Boot footprint by reusing dev->name as a driver's displayed
name. This changes boot device name (and "mmc info" output) from "EXYNOS
DWMMC" to something like "mmc@12100000".

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-08-19 16:09:06 +09:00
Sam Protsenko
06663c917f mmc: exynos_dw_mmc: Don't call dwmci_setup_cfg() after add_dwmci()
add_dwmci() is already calling dwmci_setup_cfg() internally, there is no
needed to call dwmci_setup_cfg() again in case when add_dwmci() is used
(for non-DM cases). Fix it by calling dwmci_setup_cfg() only in DM
cases, when add_dwmci() wasn't called. Also, this assignment:

    host->mmc = &plat->mmc;

is wrong in non-DM case when add_dwmci() was called, as it's creating
mmc object internally. Fix that by pulling that assignment into DM case,
when add_dwmci() isn't called.

While at it, add also this missing assignment:

    host->mmc->dev = dev;

Fixes: 3537ee879e04 ("mmc: exynos_dw_mmc: support the Driver mode for Exynos")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2024-08-19 16:09:06 +09:00