Introduce fdt_apply_ddrss_timings_patch() to allow board code to
override DDR settings in the device tree prior to DDRSS driver probing.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Tested-by: John Ma <jma@phytec.com>
Call do_board_detect() hook before the K3 DDRSS driver gets probed.
It will allow boards to adjust DDR timings in do_board_detect().
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Tested-by: John Ma <jma@phytec.com>
Functions are declared as phytec_am6* and not phytec_am62*.
Update the definitions to match the declarations.
Fixes: 9d152c23279c ("board: phytec: Add SOM detection for AM6x")
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Tested-by: John Ma <jma@phytec.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
SoM detection is using I2C driver model functions.
Let's depend on I2C.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Tested-by: John Ma <jma@phytec.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Daniel Schultz <d.schultz@phytec.de> says:
This patch series adds support for the EEPROM v3 API.
V3 is backwards compatible to V2 and therefore, the V2 image still
exists at the beginning. Only the API version changed from 2 to 3.
V3 is a block-based memory layout organized as singled-linked list
with different types of blocks. This is a more flexible approach and
allows us to extend it by more block types in the future.
The V3 data starts with a 8-byte large header which defines the
block count (u8), V3 subversion (u8) and data payload length (u16).
Additionally the header contains a CRC8 checksum a 3 reserved bytes.
Each block starts with a 4-byte large header which defined the
block type (u8), the absolute address of the next block (u16) and a
CRC8 checksum. The content itself is defined via the block type and
we currently have 2 different types:
1) MAC: Contains the Ethernet interface number (u8), MAC address
(6 x u8) and a CRC8 checksum.
Enable CONFIG_ENV_OVERWRITE to overwrite ethaddr in the environment.
This is required because our environment is not located in the
boot partition.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
Read the EEPROM API v3 content and set all available
MAC-Addresses to the environment.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
This API is based on a block structure with a 8 Byte large
API v3 header and various of different blocks following. It extends
our current API v2, which is always 32 Byte large, and is located
directly after v2.
Add the MAC block as first block type. It contains the physical
Ehternet interface number, a MAC address and a CRC checksum over the
MAC payload.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
Move the entire initialization code for API v2 into a dedicated
function. This rework will allow to easily integrate the API v3
as next step during init.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
The EEPROM image length for API v2 is fixed to 32 bytes. No need
to use sizeof while this value won't change. This value is
also be required for API v3 to know where the API v3 header starts.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
We need to read multiple times from different offsets in API v3.
Move the EEPROM read logic into a dedicated function to make it
usable multiple times.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Tested-by: Wadim Egorov <w.egorov@phytec.de>
Beleswar Padhi <b-padhi@ti.com> says:
Hello All,
This series adds remoteproc support for TI's J784S4 SoCs. The K3 J784S4
SoCs have four dual-core R5F subsystems and four C71x DSP subsystems.
Enable the remoteproc drivers in defconfig and set the rproc firmware
names to add remoteproc support.
Note: No driver changes are required as J784S4 SoCs have the same data
as J721S2 SoCs. Thus, utilize the existing compatible string for driver
probe.
Include k3_rproc.env to access rproc boot commands and specify
rproc firmware names for adding remoteproc support in J784S4 SoCs.
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
The K3 J784S4 SoC has four dual-core R5F subsystems and four C71x DSP
subsystems. Set config values to enable the remoteproc functionality
with these R5F and DSP subsystems.
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
The flag will be used for booting authenticated remote procs from hs-se
devices which can optionally be used in hs-fs devices also.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Secure firmwares must be loaded if SOC is secure,
currently rproc framework chooses non-secure firmware always.
So adding support to load secure firmware, when SOC is secure
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Remoteproc firmware images aren't authenticated in the current boot flow.
Authenticates remoteproc firmware images to complete the root of trust
in secure booting.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
ti_secure_image_post_process and ti_secure_image_check_binary is used
for the authentication purposes in the current boot flow. Authentication
of remoteproc firmware images require ti_secure_image_post_process to be
available outside mach-k3.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Neha Malcom Francis <n-francis@ti.com> says:
This series was plucked out from the larger series [1] that did some
templating reformatting and also enabled OF_UPSTREAM for J721E. The
former has been kept aside till all the platforms affected have moved to
using OF_UPSTREAM to have less conflicts while merging.
Patches split J721E EVM and J721E SK to using separate builds, as well
as enable OF_UPSTREAM for both the platforms.
Boot logs:
https://gist.github.com/nehamalcom/8f326376b6c6b1196084721405159bb9
[1] https://lore.kernel.org/all/20240322131011.1029620-1-n-francis@ti.com/
Move to using OF_UPSTREAM config and thus using the devicetree-rebasing
subtree.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Add defconfig for J721E SK R5 and A72 configuration.
This includes and modifies the J721E EVM defconfigs:
j721e_evm_r5_defconfig -> j721e_sk_r5_defconfig
j721e_evm_a72_defconfig -> j721e_sk_a72_defconfig
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Introduce k3-j721e-r5.dtsi to be used by board R5 DTS files. This
helps sync SoC changes across boards.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Emanuele Ghidoli <emanuele.ghidoli@toradex.com> says:
Manually, since SysConfig tool do not have the relevant option,
set PHY_LP4_WDQS_OE_EXTEND to 1.
Since WDQS control mode is required on our modules LPDDR4,
this enables WDQS control mode 1.
Manually, since SysConfig tool do not have the relevant option,
set PHY_LP4_WDQS_OE_EXTEND to 1.
Since WDQS control mode is required on our modules LPDDR4,
this enables WDQS control mode 1.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Update the autogenerated LPDDR4 configuration using the latest available
SysConfig tool.
This changes are cosmetic and are made to track the last used tool version.
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Marek Behún <kabel@kernel.org> says:
This series contains improvements for the 'eeprom' command:
- refactors
- fixes
- improvements
- ability to use driver model EEPROMs (uclass UCLASS_I2C_EEPROM)
- more flexible EEPROM layout support
It should not cause any behavior change for any existing board.
This series is a dependency for some DDR issue fixes for Turris Omnia.
I will be sending that one separately.
github PR link (with CI):
https://github.com/u-boot/u-boot/pull/540
- there is a failure for
test.py for sandbox sandbox_clang
but it seems unrelated to these changes
Extend the 'eeprom' command to allow accessing EEPROMs probed via
driver model, uclass UCLASS_I2C_EEPROM.
When the CONFIG_I2C_EEPROM config option is enabled (and so the
i2c-eeprom driver is built), the 'eeprom' command now accepts driver
model device name as EEPROM specifier for the 'eeprom' command, in
addition to the legacy [[bus] devaddr] specifier.
Moreover if no device specifier is given, then the first
UCLASS_I2C_EEPROM device is used, if found.
Signed-off-by: Marek Behún <kabel@kernel.org>
Don't read/write whole EEPROM if not necessary when printing / updating
EEPROM layout fields. Only read/write layout.data_size bytes.
Signed-off-by: Marek Behún <kabel@kernel.org>
Refactor the eeprom_execute_command() function into separate functions
do_eeprom_rw(), do_eeprom_print() and do_eeprom_update().
Signed-off-by: Marek Behún <kabel@kernel.org>
In preparation for allowing to access eeprom by driver-model device
name, refactor the eeprom device specifier parsing. Instead of filling
two parameters (i2c_bus, i2c_addr), the parsing function now fills one
parameter of type struct eeprom_dev_spec.
Signed-off-by: Marek Behún <kabel@kernel.org>
Add a new Kconfig option EEPROM_LAYOUT_VERSIONS, and hide eeprom
layout versionsing code behind it. Only print the relevant help in
'eeprom' command usage if this option is enabled.
Enable this new option for cm_fx6_defconfig and cm_t43_defconfig.
These are the only boards using EEPROM layout versioning.
Signed-off-by: Marek Behún <kabel@kernel.org>
The bus and devaddr arguments of the eeprom command are optional, and if
only one is given, it is assumed to be devaddr. Change the usage help
from
<bus> <devaddr>
to
[[bus] [devaddr]
Signed-off-by: Marek Behún <kabel@kernel.org>
The byte variable is of type unsigned char, it is never less than zero.
The error case is handled by *endptr, so drop the comparison altogether.
Signed-off-by: Marek Behún <kabel@kernel.org>
The __eeprom_field_update_bin() function is expected to parse a hex
string into bytes (potentially in reverse order), but the
simple_strtoul() function is given 0 as base. This does not work since
the string does not contain '0x' prefix. Add explicit base 16.
Signed-off-by: Marek Behún <kabel@kernel.org>
Split the eeprom layout field finding code from the
eeprom_layout_update_field() function in order to make it usable in
alternative implementations of update method.
Signed-off-by: Marek Behún <kabel@kernel.org>
Assign the default eeprom layout parameter .data_size and methods
.print() and .update() before calling eeprom_layout_assign() in
eeprom_layout_setup().
This allows eeprom_layout_assign() to overwrite these if needed.
Signed-off-by: Marek Behún <kabel@kernel.org>
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/20956
- Support different RAM sizes on imx8m phycoce boards.
- Support new toradex variants.
- Support Samsung 4GB DDR and Realtek RTL8211E PHY on imx8mm-cl-iot-gate.
- Convert imx8mm-phycore and imx8mp-phycore boards to use OF_UPSTREAM.
Newer versions of the imx8mm-cl-iot-gate boards may come populated with a
Samsung 4GB DDR model.
Add support for it.
Signed-off-by: Fabio Estevam <festevam@denx.de>
make it possible to set the RAM timing frequency statically independent
from the RAM size. Fixed RAM timing frequency can be used while the
RAM size is still determined by the EEPROM image.
Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
We might not be able to always rely on the EEPROM introspection data.
So add a config option alternative which configures the RAM size
to a fix value.
We still try to read the EEPROM introspection data at this point.
So we can print the SoM information if available.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Add support for different RAM sizes and speed grades on the
phyCORE-i.MX8MP.
Add support for 1GB 1.5GHz, 1GB 2GHz, 4GB 1.5GHz,
4GB 2GHz and 8GB 2GHz RAM.
The RAM size and speed grade is detected by the information
stored in the EEPROM on the SoM.
Co-developed-by: Benjamin Hahn <B.Hahn@phytec.de>
Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
Co-developed-by: Yannic Moog <y.moog@phytec.de>
Signed-off-by: Yannic Moog <y.moog@phytec.de>
Co-developed-by: Yashwanth Varakala <y.varakala@phytec.de>
Signed-off-by: Yashwanth Varakala <y.varakala@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
