sunxi: Work around lack of Linux MBUS driver

Signed-off-by: Samuel Holland <samuel@sholland.org>

Kconfig

@@ -12,6 +12,8 @@ source "scripts/Kconfig.include"
 # Allow defaults in arch-specific code to override any given here
 source "arch/Kconfig"
 
+source "board/sunxi/Kconfig"
+
 menu "General setup"
 
 config BROKEN
@@ -415,7 +417,7 @@ config BUILD_TARGET
 	default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
 	default "u-boot-elf.srec" if RCAR_GEN3
 	default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
-				ARCH_SUNXI || RISCV || ARCH_ZYNQMP)
+				RISCV || ARCH_ZYNQMP)
 	default "u-boot.kwb" if ARCH_KIRKWOOD
 	default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
 	default "u-boot-with-spl.imx" if ARCH_MX6 && SPL

Makefile

@@ -1005,6 +1005,23 @@ endif
 endif
 endif
 
+ifeq ($(CONFIG_MACH_SUN8I_H3)$(CONFIG_ARMV7_PSCI),yy)
+INPUTS-$(CONFIG_ARMV7_PSCI) += u-boot-resume.img
+
+MKIMAGEFLAGS_u-boot-resume.img := -B 0x400 -T sunxi_egon
+
+u-boot-resume.img: u-boot-resume.bin
+	$(call if_changed,mkimage)
+
+OBJCOPYFLAGS_u-boot-resume.bin := -O binary
+
+u-boot-resume.bin: u-boot-resume.o
+	$(call if_changed,objcopy)
+
+u-boot-resume.S: u-boot
+	@sed -En 's/(0x[[:xdigit:]]+) +psci_cpu_entry/ldr pc, =\1/p' $<.map > $@
+endif
+
 INPUTS-$(CONFIG_X86) += u-boot-x86-start16.bin u-boot-x86-reset16.bin \
 	$(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \
 	$(if $(CONFIG_TPL_X86_16BIT_INIT),tpl/u-boot-tpl.bin)

arch/arm/Kconfig

@@ -1194,13 +1194,17 @@ config ARCH_SUNXI
 	imply SPL_GPIO
 	imply SPL_LIBCOMMON_SUPPORT
 	imply SPL_LIBGENERIC_SUPPORT
+	imply SPL_LOAD_FIT
 	imply SPL_MMC if MMC
 	imply SPL_POWER
 	imply SPL_SERIAL
 	imply SYSRESET
 	imply SYSRESET_WATCHDOG
 	imply SYSRESET_WATCHDOG_AUTO
+	imply USB_EHCI_GENERIC
+	imply USB_ETHER if USB_MUSB_GADGET
 	imply USB_GADGET
+	imply USB_OHCI_GENERIC
 	imply WDT
 
 config ARCH_U8500

arch/arm/cpu/armv7/Kconfig

@@ -75,11 +75,14 @@ config ARMV7_PSCI
 choice
 	prompt "Supported PSCI version"
 	depends on ARMV7_PSCI
-	default ARMV7_PSCI_0_1 if ARCH_SUNXI
+	default ARMV7_PSCI_1_1 if ARCH_SUNXI
 	default ARMV7_PSCI_1_0
 	help
 	  Select the supported PSCI version.
 
+config ARMV7_PSCI_1_1
+	bool "PSCI V1.1"
+
 config ARMV7_PSCI_1_0
 	bool "PSCI V1.0"
 

arch/arm/cpu/armv7/sunxi/Makefile

@@ -13,8 +13,12 @@ obj-$(CONFIG_MACH_SUN6I)	+= sram.o
 obj-$(CONFIG_MACH_SUN8I)	+= sram.o
 
 ifndef CONFIG_SPL_BUILD
+ifdef CONFIG_MACH_SUN8I_H3
+obj-$(CONFIG_ARMV7_PSCI)	+= psci-scpi.o
+else
 obj-$(CONFIG_ARMV7_PSCI)	+= psci.o
 endif
+endif
 
 ifdef CONFIG_SPL_BUILD
 obj-y	+= fel_utils.o

arch/arm/cpu/armv7/sunxi/psci-scpi.c

@@ -0,0 +1,451 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ * Copyright (C) 2018-2021 Samuel Holland <samuel@sholland.org>
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/cpucfg.h>
+#include <asm/armv7.h>
+#include <asm/gic.h>
+#include <asm/io.h>
+#include <asm/psci.h>
+#include <asm/secure.h>
+#include <asm/system.h>
+
+#define	GICD_BASE		(SUNXI_GIC400_BASE + GIC_DIST_OFFSET)
+#define	GICC_BASE		(SUNXI_GIC400_BASE + GIC_CPU_OFFSET_A15)
+
+#define HW_ON			0
+#define HW_OFF			1
+#define HW_STANDBY		2
+
+#define MPIDR_AFFLVL0(mpidr)	(mpidr & 0xf)
+#define MPIDR_AFFLVL1(mpidr)	(mpidr >> 8 & 0xf)
+
+#define SCPI_SHMEM_BASE		0x0004be00
+#define SCPI_SHMEM		((struct scpi_shmem *)SCPI_SHMEM_BASE)
+
+#define SCPI_RX_CHANNEL		1
+#define SCPI_TX_CHANNEL		0
+#define SCPI_VIRTUAL_CHANNEL	BIT(0)
+
+#define SCPI_MESSAGE_SIZE	0x100
+#define SCPI_PAYLOAD_SIZE	(SCPI_MESSAGE_SIZE - sizeof(struct scpi_header))
+
+#define SUNXI_MSGBOX_BASE	0x01c17000
+#define REMOTE_IRQ_STAT_REG	(SUNXI_MSGBOX_BASE + 0x0050)
+#define LOCAL_IRQ_STAT_REG	(SUNXI_MSGBOX_BASE + 0x0070)
+#define MSG_STAT_REG(n)		(SUNXI_MSGBOX_BASE + 0x0140 + 0x4 * (n))
+#define MSG_DATA_REG(n)		(SUNXI_MSGBOX_BASE + 0x0180 + 0x4 * (n))
+
+#define RX_IRQ(n)		BIT(0 + 2 * (n))
+#define TX_IRQ(n)		BIT(1 + 2 * (n))
+
+enum {
+	CORE_POWER_LEVEL		= 0,
+	CLUSTER_POWER_LEVEL		= 1,
+	CSS_POWER_LEVEL			= 2,
+};
+
+enum {
+	SCPI_CMD_SCP_READY		= 0x01,
+	SCPI_CMD_SET_CSS_POWER_STATE	= 0x03,
+	SCPI_CMD_GET_CSS_POWER_STATE	= 0x04,
+	SCPI_CMD_SET_SYS_POWER_STATE	= 0x05,
+};
+
+enum {
+	SCPI_E_OK			= 0,
+	SCPI_E_PARAM			= 1,
+	SCPI_E_ALIGN			= 2,
+	SCPI_E_SIZE			= 3,
+	SCPI_E_HANDLER			= 4,
+	SCPI_E_ACCESS			= 5,
+	SCPI_E_RANGE			= 6,
+	SCPI_E_TIMEOUT			= 7,
+	SCPI_E_NOMEM			= 8,
+	SCPI_E_PWRSTATE			= 9,
+	SCPI_E_SUPPORT			= 10,
+	SCPI_E_DEVICE			= 11,
+	SCPI_E_BUSY			= 12,
+	SCPI_E_OS			= 13,
+	SCPI_E_DATA			= 14,
+	SCPI_E_STATE			= 15,
+};
+
+enum {
+	SCPI_POWER_ON			= 0x00,
+	SCPI_POWER_RETENTION		= 0x01,
+	SCPI_POWER_OFF			= 0x03,
+};
+
+enum {
+	SCPI_SYSTEM_SHUTDOWN		= 0x00,
+	SCPI_SYSTEM_REBOOT		= 0x01,
+	SCPI_SYSTEM_RESET		= 0x02,
+};
+
+struct scpi_header {
+	u8			command;
+	u8			sender;
+	u16			size;
+	u32			status;
+};
+
+struct scpi_message {
+	struct scpi_header	header;
+	u8			payload[SCPI_PAYLOAD_SIZE];
+};
+
+struct scpi_shmem {
+	struct scpi_message	rx;
+	struct scpi_message	tx;
+};
+
+static bool __secure_data gic_dist_init;
+
+static u32 __secure_data lock;
+
+static inline u32 __secure read_mpidr(void)
+{
+	u32 val;
+
+	asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
+
+	return val;
+}
+
+static void __secure scpi_begin_command(void)
+{
+	u32 mpidr = read_mpidr();
+
+	do {
+		while (readl(&lock));
+		writel(mpidr, &lock);
+		dsb();
+	} while (readl(&lock) != mpidr);
+	while (readl(REMOTE_IRQ_STAT_REG) & RX_IRQ(SCPI_TX_CHANNEL));
+}
+
+static void __secure scpi_send_command(void)
+{
+	writel(SCPI_VIRTUAL_CHANNEL, MSG_DATA_REG(SCPI_TX_CHANNEL));
+}
+
+static void __secure scpi_wait_response(void)
+{
+	while (!readl(MSG_STAT_REG(SCPI_RX_CHANNEL)));
+}
+
+static void __secure scpi_end_command(void)
+{
+	while (readl(MSG_STAT_REG(SCPI_RX_CHANNEL)))
+		readl(MSG_DATA_REG(SCPI_RX_CHANNEL));
+	writel(RX_IRQ(SCPI_RX_CHANNEL), LOCAL_IRQ_STAT_REG);
+	writel(0, &lock);
+}
+
+static void __secure scpi_set_css_power_state(u32 target_cpu, u32 core_state,
+					      u32 cluster_state, u32 css_state)
+{
+	struct scpi_shmem *shmem = SCPI_SHMEM;
+
+	scpi_begin_command();
+
+	shmem->tx.header.command = SCPI_CMD_SET_CSS_POWER_STATE;
+	shmem->tx.header.size = 4;
+
+	shmem->tx.payload[0] = target_cpu    >> 4 | target_cpu;
+	shmem->tx.payload[1] = cluster_state << 4 | core_state;
+	shmem->tx.payload[2] = css_state;
+	shmem->tx.payload[3] = 0;
+
+	scpi_send_command();
+	scpi_end_command();
+}
+
+static s32 __secure scpi_get_css_power_state(u32 target_cpu, u8 *core_states,
+					     u8 *cluster_state)
+{
+	struct scpi_shmem *shmem = SCPI_SHMEM;
+	u32 cluster = MPIDR_AFFLVL1(target_cpu);
+	u32 offset;
+	s32 ret;
+
+	scpi_begin_command();
+
+	shmem->tx.header.command = SCPI_CMD_GET_CSS_POWER_STATE;
+	shmem->tx.header.size = 0;
+
+	scpi_send_command();
+	scpi_wait_response();
+
+	for (offset = 0; offset < shmem->rx.header.size; offset += 2) {
+		if ((shmem->rx.payload[offset] & 0xf) == cluster) {
+			*cluster_state = shmem->rx.payload[offset+0] >> 4;
+			*core_states   = shmem->rx.payload[offset+1];
+
+			break;
+		}
+	}
+
+	ret = shmem->rx.header.status;
+
+	scpi_end_command();
+
+	return ret;
+}
+
+static s32 __secure scpi_set_sys_power_state(u32 sys_state)
+{
+	struct scpi_shmem *shmem = SCPI_SHMEM;
+	s32 ret;
+
+	scpi_begin_command();
+
+	shmem->tx.header.command = SCPI_CMD_SET_SYS_POWER_STATE;
+	shmem->tx.header.size = 1;
+
+	shmem->tx.payload[0] = sys_state;
+
+	scpi_send_command();
+	scpi_wait_response();
+
+	ret = shmem->rx.header.status;
+
+	scpi_end_command();
+
+	return ret;
+}
+
+void psci_enable_smp(void);
+
+static s32 __secure psci_suspend_common(u32 pc, u32 context_id, u32 core_state,
+					u32 cluster_state, u32 css_state)
+
+{
+	u32 target_cpu = read_mpidr();
+
+	if (core_state == SCPI_POWER_OFF)
+		psci_save(MPIDR_AFFLVL0(target_cpu), pc, context_id);
+	if (css_state == SCPI_POWER_OFF)
+		gic_dist_init = true;
+
+	scpi_set_css_power_state(target_cpu, core_state,
+				 cluster_state, css_state);
+
+	psci_cpu_off_common();
+
+	wfi();
+
+	psci_enable_smp();
+
+	return ARM_PSCI_RET_SUCCESS;
+}
+
+u32 __secure psci_version(void)
+{
+	return ARM_PSCI_VER_1_1;
+}
+
+s32 __secure psci_cpu_suspend(u32 __always_unused function_id,
+			      u32 power_state, u32 pc, u32 context_id)
+{
+	return psci_suspend_common(pc, context_id,
+				   power_state >> 0 & 0xf,
+				   power_state >> 4 & 0xf,
+				   power_state >> 8 & 0xf);
+}
+
+s32 __secure psci_cpu_off(void)
+{
+	u32 pc = 0, context_id = 0;
+
+	return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
+				   SCPI_POWER_OFF, SCPI_POWER_ON);
+}
+
+s32 __secure psci_cpu_on(u32 __always_unused function_id,
+			 u32 target_cpu, u32 pc, u32 context_id)
+{
+	psci_save(MPIDR_AFFLVL0(target_cpu), pc, context_id);
+
+	scpi_set_css_power_state(target_cpu, SCPI_POWER_ON,
+				 SCPI_POWER_ON, SCPI_POWER_ON);
+
+	return ARM_PSCI_RET_SUCCESS;
+}
+
+s32 __secure psci_affinity_info(u32 function_id,
+				u32 target_cpu, u32 power_level)
+{
+	if (power_level != CORE_POWER_LEVEL)
+		return ARM_PSCI_RET_INVAL;
+
+	/* This happens to have the same HW_ON/HW_OFF encoding. */
+	return psci_node_hw_state(function_id, target_cpu, power_level);
+}
+
+void __secure psci_system_off(void)
+{
+	scpi_set_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
+
+	/* Wait to be turned off. */
+	for (;;) wfi();
+}
+
+void __secure psci_system_reset(void)
+{
+	scpi_set_sys_power_state(SCPI_SYSTEM_REBOOT);
+
+	/* Wait to be turned off. */
+	for (;;) wfi();
+}
+
+s32 __secure psci_features(u32 __always_unused function_id,
+			   u32 psci_fid)
+{
+	switch (psci_fid) {
+	case ARM_PSCI_0_2_FN_PSCI_VERSION:
+	case ARM_PSCI_0_2_FN_CPU_SUSPEND:
+	case ARM_PSCI_0_2_FN_CPU_OFF:
+	case ARM_PSCI_0_2_FN_CPU_ON:
+	case ARM_PSCI_0_2_FN_AFFINITY_INFO:
+	case ARM_PSCI_0_2_FN_SYSTEM_OFF:
+	case ARM_PSCI_0_2_FN_SYSTEM_RESET:
+	case ARM_PSCI_1_0_FN_PSCI_FEATURES:
+	case ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND:
+	case ARM_PSCI_1_0_FN_NODE_HW_STATE:
+	case ARM_PSCI_1_0_FN_SYSTEM_SUSPEND:
+	case ARM_PSCI_1_1_FN_SYSTEM_RESET2:
+		return ARM_PSCI_RET_SUCCESS;
+	default:
+		return ARM_PSCI_RET_NI;
+	}
+}
+
+s32 __secure psci_cpu_default_suspend(u32 __always_unused function_id,
+				      u32 pc, u32 context_id)
+{
+	return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
+				   SCPI_POWER_OFF, SCPI_POWER_RETENTION);
+}
+
+s32 __secure psci_node_hw_state(u32 __always_unused function_id,
+				u32 target_cpu, u32 power_level)
+{
+	u32 core = MPIDR_AFFLVL0(target_cpu);
+	u8 core_states, cluster_state;
+
+	if (power_level >= CSS_POWER_LEVEL)
+		return HW_ON;
+	if (scpi_get_css_power_state(target_cpu, &core_states, &cluster_state))
+		return ARM_PSCI_RET_NI;
+	if (power_level == CLUSTER_POWER_LEVEL) {
+		if (cluster_state == SCPI_POWER_ON)
+			return HW_ON;
+		if (cluster_state < SCPI_POWER_OFF)
+			return HW_STANDBY;
+		return HW_OFF;
+	}
+
+	return (core_states & BIT(core)) ? HW_ON : HW_OFF;
+}
+
+s32 __secure psci_system_suspend(u32 __always_unused function_id,
+				 u32 pc, u32 context_id)
+{
+	return psci_suspend_common(pc, context_id, SCPI_POWER_OFF,
+				   SCPI_POWER_OFF, SCPI_POWER_OFF);
+}
+
+s32 __secure psci_system_reset2(u32 __always_unused function_id,
+				u32 reset_type, u32 cookie)
+{
+	s32 ret;
+
+	if (reset_type)
+		return ARM_PSCI_RET_INVAL;
+
+	ret = scpi_set_sys_power_state(SCPI_SYSTEM_RESET);
+	if (ret)
+		return ARM_PSCI_RET_INVAL;
+
+	/* Wait to be turned off. */
+	for (;;) wfi();
+}
+
+/*
+ * R40 is different from other single cluster SoCs. The secondary core
+ * entry address register is in the SRAM controller address range.
+ */
+#define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0		(0xbc)
+
+#ifdef CONFIG_MACH_SUN8I_R40
+/* secondary core entry address is programmed differently on R40 */
+static void __secure sunxi_set_entry_address(void *entry)
+{
+	writel((u32)entry,
+	       SUNXI_SRAMC_BASE + SUN8I_R40_SRAMC_SOFT_ENTRY_REG0);
+}
+#else
+static void __secure sunxi_set_entry_address(void *entry)
+{
+	struct sunxi_cpucfg_reg *cpucfg =
+		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
+
+	writel((u32)entry, &cpucfg->priv0);
+
+	if (IS_ENABLED(CONFIG_MACH_SUN8I_H3)) {
+		/* Redirect CPU 0 to the secure monitor via the resume shim. */
+		writel(0x16aaefe8, &cpucfg->super_standy_flag);
+		writel(0xaa16efe8, &cpucfg->super_standy_flag);
+		writel(SUNXI_RESUME_BASE, &cpucfg->priv1);
+	}
+}
+#endif
+
+void __secure psci_arch_init(void)
+{
+	static bool __secure_data one_time_init = true;
+
+	if (one_time_init) {
+		/* Set secondary core power-on PC. */
+		sunxi_set_entry_address(psci_cpu_entry);
+
+		/* Wait for the SCP firmware to boot. */
+		scpi_begin_command();
+		scpi_wait_response();
+		scpi_end_command();
+
+		one_time_init = false;
+	}
+
+	/*
+	 * Copied from arch/arm/cpu/armv7/virt-v7.c
+	 * See also gic_resume() in arch/arm/mach-imx/mx7/psci-mx7.c
+	 */
+	if (gic_dist_init) {
+		u32 i, itlinesnr;
+
+		/* enable the GIC distributor */
+		writel(readl(GICD_BASE + GICD_CTLR) | 0x03, GICD_BASE + GICD_CTLR);
+
+		/* TYPER[4:0] contains an encoded number of available interrupts */
+		itlinesnr = readl(GICD_BASE + GICD_TYPER) & 0x1f;
+
+		/* set all bits in the GIC group registers to one to allow access
+		 * from non-secure state. The first 32 interrupts are private per
+		 * CPU and will be set later when enabling the GIC for each core
+		 */
+		for (i = 1; i <= itlinesnr; i++)
+			writel((unsigned)-1, GICD_BASE + GICD_IGROUPRn + 4 * i);
+
+		gic_dist_init = false;
+	}
+
+	/* Be cool with non-secure. */
+	writel(0xff, GICC_BASE + GICC_PMR);
+}

arch/arm/cpu/armv7/sunxi/psci.c

@@ -10,6 +10,7 @@
 #include <common.h>
 #include <asm/cache.h>
 
+#include <asm/arch/clock.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/cpucfg.h>
 #include <asm/arch/prcm.h>
@@ -38,6 +39,15 @@
 #define SUN8I_R40_PWR_CLAMP(cpu)		(0x120 + (cpu) * 0x4)
 #define SUN8I_R40_SRAMC_SOFT_ENTRY_REG0		(0xbc)
 
+static inline u32 __secure cp15_read_mpidr(void)
+{
+	u32 val;
+
+	asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (val));
+
+	return val;
+}
+
 static void __secure cp15_write_cntp_tval(u32 tval)
 {
 	asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
@@ -132,6 +142,13 @@ static void __secure sunxi_set_entry_address(void *entry)
 		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
 
 	writel((u32)entry, &cpucfg->priv0);
+
+#ifdef CONFIG_MACH_SUN8I_H3
+	/* Redirect CPU 0 to the secure monitor via the resume shim. */
+	writel(0x16aaefe8, &cpucfg->super_standy_flag);
+	writel(0xaa16efe8, &cpucfg->super_standy_flag);
+	writel(SUNXI_RESUME_BASE, &cpucfg->priv1);
+#endif
 }
 #endif
 
@@ -246,9 +263,12 @@ out:
 int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
 			 u32 context_id)
 {
+	struct sunxi_ccm_reg *ccu = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 	struct sunxi_cpucfg_reg *cpucfg =
 		(struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE;
 	u32 cpu = (mpidr & 0x3);
+	u32 cpu_clk;
+	u32 bus_clk;
 
 	/* store target PC and context id */
 	psci_save(cpu, pc, context_id);
@@ -265,12 +285,32 @@ int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc,
 	/* Lock CPU (Disable external debug access) */
 	clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
 
+	if (IS_ENABLED(CONFIG_MACH_SUN8I_H3) && cpu == 0) {
+		/* Save registers that will be clobbered by the BROM. */
+		cpu_clk = readl(&ccu->cpu_axi_cfg);
+		bus_clk = readl(&ccu->ahb1_apb1_div);
+
+		/* Bypass PLL_PERIPH0 so AHB1 frequency does not spike. */
+		setbits_le32(&ccu->pll6_cfg, BIT(25));
+	}
+
 	/* Power up target CPU */
 	sunxi_cpu_set_power(cpu, true);
 
 	/* De-assert reset on target CPU */
 	writel(BIT(1) | BIT(0), &cpucfg->cpu[cpu].rst);
 
+	if (IS_ENABLED(CONFIG_MACH_SUN8I_H3) && cpu == 0) {
+		/* Spin until the BROM has clobbered the clock registers. */
+		while (readl(&ccu->ahb1_apb1_div) != 0x00001100);
+
+		/* Restore the registers and turn off PLL_PERIPH0 bypass. */
+		writel(cpu_clk, &ccu->cpu_axi_cfg);
+		writel(bus_clk, &ccu->ahb1_apb1_div);
+
+		clrbits_le32(&ccu->pll6_cfg, BIT(25));
+	}
+
 	/* Unlock CPU (Disable external debug access) */
 	setbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu));
 
@@ -281,9 +321,14 @@ s32 __secure psci_cpu_off(void)
 {
 	psci_cpu_off_common();
 
+	if (cp15_read_mpidr() & 3) {
 		/* Ask CPU0 via SGI15 to pull the rug... */
 		writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
 		dsb();
+	} else {
+		/* Unmask FIQs to service SGI15. */
+		asm volatile ("cpsie f");
+	}
 
 	/* Wait to be turned off */
 	while (1)

arch/arm/cpu/armv8/fwcall.c

@@ -103,7 +103,7 @@ void __noreturn psci_system_reset2(u32 reset_level, u32 cookie)
 {
 	struct pt_regs regs;
 
-	regs.regs[0] = ARM_PSCI_0_2_FN64_SYSTEM_RESET2;
+	regs.regs[0] = ARM_PSCI_1_1_FN64_SYSTEM_RESET2;
 	regs.regs[1] = PSCI_RESET2_TYPE_VENDOR | reset_level;
 	regs.regs[2] = cookie;
 	if (use_smc_for_psci)

arch/arm/dts/Makefile

@@ -539,7 +539,8 @@ dtb-$(CONFIG_MACH_SUN4I) += \
 	sun4i-a10-olinuxino-lime.dtb \
 	sun4i-a10-pcduino.dtb \
 	sun4i-a10-pcduino2.dtb \
-	sun4i-a10-pov-protab2-ips9.dtb
+	sun4i-a10-pov-protab2-ips9.dtb \
+	sun4i-a10-topwise-a721.dtb
 dtb-$(CONFIG_MACH_SUN5I) += \
 	sun5i-a10s-auxtek-t003.dtb \
 	sun5i-a10s-auxtek-t004.dtb \
@@ -625,6 +626,7 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \
 	sun8i-a33-et-q8-v1.6.dtb \
 	sun8i-a33-ga10h-v1.1.dtb \
 	sun8i-a33-inet-d978-rev2.dtb \
+	sun8i-a33-inet-u70b-rev1.dtb \
 	sun8i-a33-ippo-q8h-v1.2.dtb \
 	sun8i-a33-olinuxino.dtb \
 	sun8i-a33-q8-tablet.dtb \

arch/arm/dts/axp209.dtsi

@@ -53,7 +53,7 @@
 	interrupt-controller;
 	#interrupt-cells = <1>;
 
-	ac_power_supply: ac-power-supply {
+	ac_power_supply: ac-power {
 		compatible = "x-powers,axp202-ac-power-supply";
 		status = "disabled";
 	};
@@ -69,7 +69,7 @@
 		#gpio-cells = <2>;
 	};
 
-	battery_power_supply: battery-power-supply {
+	battery_power_supply: battery-power {
 		compatible = "x-powers,axp209-battery-power-supply";
 		status = "disabled";
 	};
@@ -112,7 +112,7 @@
 		};
 	};
 
-	usb_power_supply: usb-power-supply {
+	usb_power_supply: usb-power {
 		compatible = "x-powers,axp202-usb-power-supply";
 		status = "disabled";
 	};

arch/arm/dts/axp22x.dtsi

@@ -67,6 +67,12 @@
 		status = "disabled";
 	};
 
+	axp_gpio: gpio {
+		compatible = "x-powers,axp221-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	regulators {
 		/* Default work frequency for buck regulators */
 		x-powers,dcdc-freq = <3000>;

arch/arm/dts/axp809.dtsi

@@ -50,4 +50,11 @@
 	compatible = "x-powers,axp809";
 	interrupt-controller;
 	#interrupt-cells = <1>;
+
+	axp_gpio: gpio {
+		compatible = "x-powers,axp809-gpio",
+			     "x-powers,axp221-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
 };

arch/arm/dts/sun4i-a10-a1000.dts

@@ -60,15 +60,26 @@
 		stdout-path = "serial0:115200n8";
 	};
 
+	hdmi-connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
 	leds {
 		compatible = "gpio-leds";
 
-		red {
+		led-0 {
 			label = "a1000:red:usr";
 			gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>;
 		};
 
-		blue {
+		led-1 {
 			label = "a1000:blue:pwr";
 			gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
@@ -125,7 +136,7 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&phy1>;
 	status = "okay";
 };
 
@@ -133,6 +144,20 @@
 	status = "okay";
 };
 
+&de {
+	status = "okay";
+};
+
+&hdmi {
+	status = "okay";
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
 &i2c0 {
 	status = "okay";
 

arch/arm/dts/sun4i-a10-ba10-tvbox.dts

@@ -68,7 +68,7 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&phy1>;
 	status = "okay";
 };
 

arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts

@@ -131,20 +131,6 @@
 	status = "okay";
 };
 
-&pio {
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-		pins = "PH5";
-		function = "gpio_in";
-		bias-pull-down;
-	};
-};
-
 &reg_usb0_vbus {
 	status = "okay";
 };
@@ -165,10 +151,8 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
-	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+	usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
-	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-	usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
 	usb0_vbus-supply = <&reg_usb0_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;
 	status = "okay";

arch/arm/dts/sun4i-a10-cubieboard.dts

@@ -75,12 +75,12 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&led_pins_cubieboard>;
 
-		blue {
+		led-0 {
 			label = "cubieboard:blue:usr";
 			gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* LED1 */
 		};
 
-		green {
+		led-1 {
 			label = "cubieboard:green:usr";
 			gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* LED2 */
 			linux,default-trigger = "heartbeat";
@@ -114,7 +114,7 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&phy1>;
 	status = "okay";
 };
 
@@ -184,12 +184,6 @@
 		function = "gpio_out";
 		drive-strength = <20>;
 	};
-
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
 };
 
 &reg_ahci_5v {
@@ -254,9 +248,7 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
-	pinctrl-0 = <&usb0_id_detect_pin>;
-	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
 	usb1_vbus-supply = <&reg_usb1_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;
 	status = "okay";

arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts

@@ -62,6 +62,7 @@
 		brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
 		default-brightness-level = <8>;
 		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+		power-supply = <&reg_vcc3v3>;
 	};
 
 	chosen {
@@ -158,20 +159,6 @@
 	status = "okay";
 };
 
-&pio {
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-		pins = "PH5";
-		function = "gpio_in";
-		bias-pull-down;
-	};
-};
-
 &pwm {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pwm0_pin>;
@@ -223,10 +210,8 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
-	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+	usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
-	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-	usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
 	usb0_vbus-supply = <&reg_usb0_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;
 	status = "okay";

arch/arm/dts/sun4i-a10-hackberry.dts

@@ -80,7 +80,7 @@
 };
 
 &emac {
-	phy = <&phy0>;
+	phy-handle = <&phy0>;
 	status = "okay";
 };
 

arch/arm/dts/sun4i-a10-hyundai-a7hd.dts

@@ -86,20 +86,6 @@
 	status = "okay";
 };
 
-&pio {
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-		pins = "PH5";
-		function = "gpio_in";
-		bias-pull-down;
-	};
-};
-
 &reg_usb0_vbus {
 	status = "okay";
 };
@@ -121,10 +107,8 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
-	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+	usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
-	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-	usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
 	usb0_vbus-supply = <&reg_usb0_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;
 	status = "okay";

arch/arm/dts/sun4i-a10-inet1.dts

@@ -62,6 +62,7 @@
 		brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
 		default-brightness-level = <8>;
 		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+		power-supply = <&reg_vcc3v3>;
 	};
 
 	chosen {
@@ -164,20 +165,6 @@
 	status = "okay";
 };
 
-&pio {
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-		pins = "PH5";
-		function = "gpio_in";
-		bias-pull-down;
-	};
-};
-
 &pwm {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pwm0_pin>;
@@ -233,10 +220,8 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
-	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+	usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
-	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-	usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
 	usb0_vbus-supply = <&reg_usb0_vbus>;
 	usb1_vbus-supply = <&reg_usb1_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;

arch/arm/dts/sun4i-a10-inet9f-rev03.dts

@@ -61,10 +61,6 @@
 
 	gpio-keys {
 		compatible = "gpio-keys-polled";
-		pinctrl-names = "default";
-		pinctrl-0 = <&key_pins_inet9f>;
-		#address-cells = <1>;
-		#size-cells = <0>;
 		poll-interval = <20>;
 
 		left-joystick-left {
@@ -72,7 +68,7 @@
 			linux,code = <ABS_X>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <0xffffffff>; /* -1 */
-			gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */
+			gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */
 		};
 
 		left-joystick-right {
@@ -80,7 +76,7 @@
 			linux,code = <ABS_X>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <1>;
-			gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */
+			gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */
 		};
 
 		left-joystick-up {
@@ -88,7 +84,7 @@
 			linux,code = <ABS_Y>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <0xffffffff>; /* -1 */
-			gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
+			gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */
 		};
 
 		left-joystick-down {
@@ -96,7 +92,7 @@
 			linux,code = <ABS_Y>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <1>;
-			gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */
+			gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */
 		};
 
 		right-joystick-left {
@@ -104,7 +100,7 @@
 			linux,code = <ABS_Z>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <0xffffffff>; /* -1 */
-			gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */
+			gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */
 		};
 
 		right-joystick-right {
@@ -112,7 +108,7 @@
 			linux,code = <ABS_Z>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <1>;
-			gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */
+			gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */
 		};
 
 		right-joystick-up {
@@ -120,7 +116,7 @@
 			linux,code = <ABS_RZ>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <0xffffffff>; /* -1 */
-			gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */
+			gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */
 		};
 
 		right-joystick-down {
@@ -128,7 +124,7 @@
 			linux,code = <ABS_RZ>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <1>;
-			gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
+			gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */
 		};
 
 		dpad-left {
@@ -136,7 +132,7 @@
 			linux,code = <ABS_HAT0X>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <0xffffffff>; /* -1 */
-			gpios = <&pio 7 23 GPIO_ACTIVE_LOW>; /* PH23 */
+			gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */
 		};
 
 		dpad-right {
@@ -144,7 +140,7 @@
 			linux,code = <ABS_HAT0X>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <1>;
-			gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */
+			gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */
 		};
 
 		dpad-up {
@@ -152,7 +148,7 @@
 			linux,code = <ABS_HAT0Y>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <0xffffffff>; /* -1 */
-			gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */
+			gpios = <&pio 7 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH25 */
 		};
 
 		dpad-down {
@@ -160,55 +156,55 @@
 			linux,code = <ABS_HAT0Y>;
 			linux,input-type = <EV_ABS>;
 			linux,input-value = <1>;
-			gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */
+			gpios = <&pio 7 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH26 */
 		};
 
 		x {
 			label = "Button X";
 			linux,code = <BTN_X>;
-			gpios = <&pio 0 16 GPIO_ACTIVE_LOW>; /* PA16 */
+			gpios = <&pio 0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA16 */
 		};
 
 		y {
 			label = "Button Y";
 			linux,code = <BTN_Y>;
-			gpios = <&pio 0 14 GPIO_ACTIVE_LOW>; /* PA14 */
+			gpios = <&pio 0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA14 */
 		};
 
 		a {
 			label = "Button A";
 			linux,code = <BTN_A>;
-			gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */
+			gpios = <&pio 0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA17 */
 		};
 
 		b {
 			label = "Button B";
 			linux,code = <BTN_B>;
-			gpios = <&pio 0 15 GPIO_ACTIVE_LOW>; /* PA15 */
+			gpios = <&pio 0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA15 */
 		};
 
 		select {
 			label = "Select Button";
 			linux,code = <BTN_SELECT>;
-			gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */
+			gpios = <&pio 0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA11 */
 		};
 
 		start {
 			label = "Start Button";
 			linux,code = <BTN_START>;
-			gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */
+			gpios = <&pio 0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA12 */
 		};
 
 		top-left {
 			label = "Top Left Button";
 			linux,code = <BTN_TL>;
-			gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
+			gpios = <&pio 7 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH22 */
 		};
 
 		top-right {
 			label = "Top Right Button";
 			linux,code = <BTN_TR>;
-			gpios = <&pio 0 13 GPIO_ACTIVE_LOW>; /* PA13 */
+			gpios = <&pio 0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA13 */
 		};
 	};
 };
@@ -308,30 +304,6 @@
 	status = "okay";
 };
 
-&pio {
-	key_pins_inet9f: key-pins {
-		pins = "PA0", "PA1", "PA3", "PA4",
-		       "PA5", "PA6", "PA8", "PA9",
-		       "PA11", "PA12", "PA13",
-		       "PA14", "PA15", "PA16", "PA17",
-		       "PH22", "PH23", "PH24", "PH25", "PH26";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-		pins = "PH5";
-		function = "gpio_in";
-		bias-pull-down;
-	};
-};
-
 &reg_dcdc2 {
 	regulator-always-on;
 	regulator-min-microvolt = <1000000>;
@@ -377,10 +349,8 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
-	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+	usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
-	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-	usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
 	usb0_vbus-supply = <&reg_usb0_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;
 	status = "okay";

arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts

@@ -58,7 +58,7 @@
 &emac {
 	pinctrl-names = "default";
 	pinctrl-0 = <&emac_pins>;
-	phy = <&phy1>;
+	phy-handle = <&phy1>;
 	status = "okay";
 };
 

arch/arm/dts/sun4i-a10-jesurun-q5.dts

@@ -63,7 +63,7 @@
 	leds {
 		compatible = "gpio-leds";
 
-		green {
+		led {
 			label = "q5:green:usr";
 			gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;  /* PH20 */
 		};
@@ -94,7 +94,7 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&phy1>;
 	status = "okay";
 };
 

arch/arm/dts/sun4i-a10-marsboard.dts

@@ -62,22 +62,22 @@
 	leds {
 		compatible = "gpio-leds";
 
-		red1 {
+		led-0 {
 			label = "marsboard:red1:usr";
 			gpios = <&pio 1 5 GPIO_ACTIVE_HIGH>;
 		};
 
-		red2 {
+		led-1 {
 			label = "marsboard:red2:usr";
 			gpios = <&pio 1 6 GPIO_ACTIVE_HIGH>;
 		};
 
-		red3 {
+		led-2 {
 			label = "marsboard:red3:usr";
 			gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>;
 		};
 
-		red4 {
+		led-3 {
 			label = "marsboard:red4:usr";
 			gpios = <&pio 1 8 GPIO_ACTIVE_HIGH>;
 		};
@@ -105,7 +105,7 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&phy1>;
 	status = "okay";
 };
 
@@ -148,14 +148,6 @@
 	status = "okay";
 };
 
-&pio {
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-};
-
 &reg_usb1_vbus {
 	status = "okay";
 };
@@ -183,9 +175,7 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
-	pinctrl-0 = <&usb0_id_detect_pin>;
-	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
 	usb1_vbus-supply = <&reg_usb1_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;
 	status = "okay";

arch/arm/dts/sun4i-a10-olinuxino-lime.dts

@@ -74,7 +74,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&led_pins_olinuxinolime>;
 
-		green {
+		led {
 			label = "a10-olinuxino-lime:green:usr";
 			gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
 			default-state = "on";
@@ -91,12 +91,11 @@
 	/*
 	 * The A10-Lime is known to be unstable when running at 1008 MHz
 	 */
-	operating-points = <
+	operating-points =
 		/* kHz	  uV */
-		912000  1350000
+		<912000	1350000>,
-		864000  1300000
+		<864000	1300000>,
-		624000  1250000
+		<624000	1250000>;
-		>;
 };
 
 &de {
@@ -112,7 +111,7 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&phy1>;
 	status = "okay";
 };
 
@@ -186,18 +185,6 @@
 		function = "gpio_out";
 		drive-strength = <20>;
 	};
-
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-		pins = "PH5";
-		function = "gpio_in";
-		bias-pull-down;
-	};
 };
 
 &reg_ahci_5v {
@@ -229,10 +216,8 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
-	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+	usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH5 */
-	usb0_id_det-gpio   = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-	usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
 	usb0_vbus-supply   = <&reg_usb0_vbus>;
 	usb1_vbus-supply = <&reg_usb1_vbus>;
 	usb2_vbus-supply = <&reg_usb2_vbus>;

arch/arm/dts/sun4i-a10-pcduino.dts

@@ -63,12 +63,12 @@
 	leds {
 		compatible = "gpio-leds";
 
-		tx {
+		led-0 {
 			label = "pcduino:green:tx";
 			gpios = <&pio 7 15 GPIO_ACTIVE_LOW>;
 		};
 
-		rx {
+		led-1 {
 			label = "pcduino:green:rx";
 			gpios = <&pio 7 16 GPIO_ACTIVE_LOW>;
 		};
@@ -76,8 +76,6 @@
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		#address-cells = <1>;
-		#size-cells = <0>;
 
 		back {
 			label = "Key Back";
@@ -112,7 +110,7 @@
 };
 
 &emac {
-	phy = <&phy1>;
+	phy-handle = <&phy1>;
 	status = "okay";
 };
 
@@ -156,14 +154,6 @@
 	status = "okay";
 };
 
-&pio {
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-};
-
 #include "axp209.dtsi"
 
 &reg_dcdc2 {
@@ -203,9 +193,7 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
-	pinctrl-0 = <&usb0_id_detect_pin>;
-	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
 	usb1_vbus-supply = <&reg_vcc5v0>; /* USB1 VBUS is always on */
 	usb2_vbus-supply = <&reg_vcc5v0>; /* USB2 VBUS is always on */
 	status = "okay";

arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts

@@ -62,6 +62,7 @@
 		brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
 		default-brightness-level = <8>;
 		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+		power-supply = <&reg_vcc3v3>;
 	};
 
 	chosen {
@@ -146,20 +147,6 @@
 	status = "okay";
 };
 
-&pio {
-	usb0_id_detect_pin: usb0-id-detect-pin {
-		pins = "PH4";
-		function = "gpio_in";
-		bias-pull-up;
-	};
-
-	usb0_vbus_detect_pin: usb0-vbus-detect-pin {
-		pins = "PH5";
-		function = "gpio_in";
-		bias-pull-down;
-	};
-};
-
 &pwm {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pwm0_pin>;
@@ -211,10 +198,8 @@
 };
 
 &usbphy {
-	pinctrl-names = "default";
+	usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
-	pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+	usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
-	usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-	usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
 	usb0_vbus-supply = <&reg_usb0_vbus>;
 	usb1_vbus-supply = <&reg_usb1_vbus>;
 	status = "okay";

arch/arm/dts/sun4i-a10-topwise-a721.dts

@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Pascal Roeleven <dev@pascalroeleven.nl>
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+	model = "Topwise A721";
+	compatible = "topwise,a721", "allwinner,sun4i-a10";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 100000 PWM_POLARITY_INVERTED>;
+		power-supply = <&reg_vbat>;
+		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+		brightness-levels = <0 30 40 50 60 70 80 90 100>;
+		default-brightness-level = <8>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	panel {
+		compatible = "starry,kr070pe2t";
+		backlight = <&backlight>;
+		power-supply = <&reg_lcd_power>;
+
+		port {
+			panel_input: endpoint {
+				remote-endpoint = <&tcon0_out_panel>;
+			};
+		};
+	};
+
+	reg_lcd_power: reg-lcd-power {
+		compatible = "regulator-fixed";
+		regulator-name = "reg-lcd-power";
+		gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
+		enable-active-high;
+	};
+
+	reg_vbat: reg-vbat {
+		compatible = "regulator-fixed";
+		regulator-name = "vbat";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+	};
+
+};
+
+&codec {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&reg_dcdc2>;
+};
+
+&de {
+	status = "okay";
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	axp209: pmic@34 {
+		reg = <0x34>;
+		interrupts = <0>;
+	};
+};
+
+#include "axp209.dtsi"
+
+&ac_power_supply {
+	status = "okay";
+};
+
+&battery_power_supply {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+
+	accelerometer@4c {
+		compatible = "fsl,mma7660";
+		reg = <0x4c>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+
+	touchscreen@38 {
+		compatible = "edt,edt-ft5406";
+		reg = <0x38>;
+		interrupt-parent = <&pio>;
+		interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>;
+		touchscreen-size-x = <800>;
+		touchscreen-size-y = <480>;
+		vcc-supply = <&reg_vcc3v3>;
+	};
+};
+
+&lradc {
+	vref-supply = <&reg_ldo2>;
+	status = "okay";
+
+	button-571 {
+		label = "Volume Up";
+		linux,code = <KEY_VOLUMEUP>;
+		channel = <0>;
+		voltage = <571428>;
+	};
+
+	button-761 {
+		label = "Volume Down";
+		linux,code = <KEY_VOLUMEDOWN>;
+		channel = <0>;
+		voltage = <761904>;
+	};
+};
+
+&mmc0 {
+	vmmc-supply = <&reg_vcc3v3>;
+	bus-width = <4>;
+	cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */
+	status = "okay";
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&otg_sram {
+	status = "okay";
+};
+
+&pio {
+	vcc-pb-supply = <&reg_vcc3v3>;
+	vcc-pf-supply = <&reg_vcc3v3>;
+	vcc-ph-supply = <&reg_vcc3v3>;
+};
+
+&pwm {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm0_pin>;
+	status = "okay";
+};
+
+&reg_dcdc2 {
+	regulator-always-on;
+	regulator-min-microvolt = <1000000>;
+	regulator-max-microvolt = <1400000>;
+	regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+	regulator-always-on;
+	regulator-min-microvolt = <1250000>;
+	regulator-max-microvolt = <1250000>;
+	regulator-name = "vdd-int-dll";
+};
+
+&reg_ldo1 {
+	regulator-name = "vdd-rtc";
+};
+
+&reg_ldo2 {
+	regulator-always-on;
+	regulator-min-microvolt = <3000000>;
+	regulator-max-microvolt = <3000000>;
+	regulator-name = "avcc";
+};
+
+&reg_usb0_vbus {
+	status = "okay";
+};
+
+&reg_usb1_vbus {
+	status = "okay";
+};
+
+&reg_usb2_vbus {
+	status = "okay";
+};
+
+&tcon0_out {
+	tcon0_out_panel: endpoint@0 {
+		reg = <0>;
+		remote-endpoint = <&panel_input>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pb_pins>;
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usb_power_supply {
+	status = "okay";
+};
+
+&usbphy {
+	usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+	usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+	usb0_vbus-supply = <&reg_usb0_vbus>;
+	usb1_vbus-supply = <&reg_usb1_vbus>;
+	usb2_vbus-supply = <&reg_usb2_vbus>;
+	status = "okay";
+};

arch/arm/dts/sun4i-a10.dtsi

@@ -115,13 +115,12 @@
 			reg = <0x0>;
 			clocks = <&ccu CLK_CPU>;
 			clock-latency = <244144>; /* 8 32k periods */
-			operating-points = <
+			operating-points =
 				/* kHz	  uV */
-				1008000 1400000
+				<1008000 1400000>,
-				912000	1350000
+				<912000	1350000>,
-				864000	1300000
+				<864000	1300000>,
-				624000	1250000
+				<624000	1250000>;
-				>;
 			#cooling-cells = <2>;
 		};
 	};
@@ -143,7 +142,7 @@
 			trips {
 				cpu_alert0: cpu-alert0 {
 					/* milliCelsius */
-					temperature = <850000>;
+					temperature = <85000>;
 					hysteresis = <2000>;
 					type = "passive";
 				};
@@ -184,14 +183,34 @@
 		status = "disabled";
 	};
 
+	pmu {
+		compatible = "arm,cortex-a8-pmu";
+		interrupts = <3>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
+		default-pool {
+			compatible = "shared-dma-pool";
+			size = <0x6000000>;
+			alloc-ranges = <0x40000000 0x10000000>;
+			reusable;
+			linux,cma-default;
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
 
-		sram-controller@1c00000 {
+		system-control@1c00000 {
-			compatible = "allwinner,sun4i-a10-sram-controller";
+			compatible = "allwinner,sun4i-a10-system-control";
 			reg = <0x01c00000 0x30>;
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -224,6 +243,19 @@
 					status = "disabled";
 				};
 			};
+
+			sram_c: sram@1d00000 {
+				compatible = "mmio-sram";
+				reg = <0x01d00000 0xd0000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x01d00000 0xd0000>;
+
+				ve_sram: sram-section@0 {
+					compatible = "allwinner,sun4i-a10-sram-c1";
+					reg = <0x000000 0x80000>;
+				};
+			};
 		};
 
 		dma: dma-controller@1c02000 {
@@ -234,7 +266,7 @@
 			#dma-cells = <2>;
 		};
 
-		nfc: nand@1c03000 {
+		nfc: nand-controller@1c03000 {
 			compatible = "allwinner,sun4i-a10-nand";
 			reg = <0x01c03000 0x1000>;
 			interrupts = <37>;
@@ -309,6 +341,7 @@
 				      "tcon-ch0",
 				      "tcon-ch1";
 			clock-output-names = "tcon0-pixel-clock";
+			#clock-cells = <0>;
 			dmas = <&dma SUN4I_DMA_DEDICATED 14>;
 
 			ports {
@@ -358,6 +391,7 @@
 				      "tcon-ch0",
 				      "tcon-ch1";
 			clock-output-names = "tcon1-pixel-clock";
+			#clock-cells = <0>;
 			dmas = <&dma SUN4I_DMA_DEDICATED 15>;
 
 			ports {
@@ -394,6 +428,17 @@
 			};
 		};
 
+		video-codec@1c0e000 {
+			compatible = "allwinner,sun4i-a10-video-engine";
+			reg = <0x01c0e000 0x1000>;
+			clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
+				 <&ccu CLK_DRAM_VE>;
+			clock-names = "ahb", "mod", "ram";
+			resets = <&ccu RST_VE>;
+			interrupts = <53>;
+			allwinner,sram = <&ve_sram 1>;
+		};
+
 		mmc0: mmc@1c0f000 {
 			compatible = "allwinner,sun4i-a10-mmc";
 			reg = <0x01c0f000 0x1000>;
@@ -450,13 +495,14 @@
 			phy-names = "usb";
 			extcon = <&usbphy 0>;
 			allwinner,sram = <&otg_sram 1>;
+			dr_mode = "otg";
 			status = "disabled";
 		};
 
 		usbphy: phy@1c13400 {
 			#phy-cells = <1>;
 			compatible = "allwinner,sun4i-a10-usb-phy";
-			reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
+			reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
 			reg-names = "phy_ctrl", "pmu1", "pmu2";
 			clocks = <&ccu CLK_USB_PHY>;
 			clock-names = "usb_phy";
@@ -530,8 +576,6 @@
 				};
 
 				hdmi_out: port@1 {
-					#address-cells = <1>;
-					#size-cells = <0>;
 					reg = <1>;
 				};
 			};
@@ -579,6 +623,16 @@
 			status = "disabled";
 		};
 
+		csi1: csi@1c1d000 {
+			compatible = "allwinner,sun4i-a10-csi1";
+			reg = <0x01c1d000 0x1000>;
+			interrupts = <43>;
+			clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
+			clock-names = "bus", "ram";
+			resets = <&ccu RST_CSI1>;
+			status = "disabled";
+		};
+
 		spi3: spi@1c1f000 {
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c1f000 0x1000>;
@@ -625,6 +679,31 @@
 				function = "can";
 			};
 
+			/omit-if-no-ref/
+			csi1_8bits_pg_pins: csi1-8bits-pg-pins {
+				pins = "PG0", "PG2", "PG3", "PG4", "PG5",
+				       "PG6", "PG7", "PG8", "PG9", "PG10",
+				       "PG11";
+				function = "csi1";
+			};
+
+			/omit-if-no-ref/
+			csi1_24bits_ph_pins: csi1-24bits-ph-pins {
+				pins = "PH0", "PH1", "PH2", "PH3", "PH4",
+				       "PH5", "PH6", "PH7", "PH8", "PH9",
+				       "PH10", "PH11", "PH12", "PH13", "PH14",
+				       "PH15", "PH16", "PH17", "PH18", "PH19",
+				       "PH20", "PH21", "PH22", "PH23", "PH24",
+				       "PH25", "PH26", "PH27";
+				function = "csi1";
+			};
+
+			/omit-if-no-ref/
+			csi1_clk_pg_pin: csi1-clk-pg-pin {
+				pins = "PG1";
+				function = "csi1";
+			};
+
 			emac_pins: emac0-pins {
 				pins = "PA0", "PA1", "PA2",
 				       "PA3", "PA4", "PA5", "PA6",
@@ -762,13 +841,20 @@
 		timer@1c20c00 {
 			compatible = "allwinner,sun4i-a10-timer";
 			reg = <0x01c20c00 0x90>;
-			interrupts = <22>;
+			interrupts = <22>,
+				     <23>,
+				     <24>,
+				     <25>,
+				     <67>,
+				     <68>;
 			clocks = <&osc24M>;
 		};
 
 		wdt: watchdog@1c20c90 {
 			compatible = "allwinner,sun4i-a10-wdt";
 			reg = <0x01c20c90 0x10>;
+			interrupts = <24>;
+			clocks = <&osc24M>;
 		};
 
 		rtc: rtc@1c20d00 {
@@ -1001,6 +1087,27 @@
 			status = "disabled";
 		};
 
+		mali: gpu@1c40000 {
+			compatible = "allwinner,sun4i-a10-mali", "arm,mali-400";
+			reg = <0x01c40000 0x10000>;
+			interrupts = <69>,
+				     <70>,
+				     <71>,
+				     <72>,
+				     <73>;
+			interrupt-names = "gp",
+					  "gpmmu",
+					  "pp0",
+					  "ppmmu0",
+					  "pmu";
+			clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
+			clock-names = "bus", "core";
+			resets = <&ccu RST_GPU>;
+
+			assigned-clocks = <&ccu CLK_GPU>;
+			assigned-clock-rates = <384000000>;
+		};
+
 		fe0: display-frontend@1e00000 {
 			compatible = "allwinner,sun4i-a10-display-frontend";
 			reg = <0x01e00000 0x20000>;

arch/arm/dts/sun50i-h6-pine-h64.dts

@@ -89,6 +89,10 @@
 	status = "okay";
 };
 
+&dwc3 {
+	status = "okay";
+};
+
 &ehci0 {
 	status = "okay";
 };
@@ -332,3 +336,7 @@
 	usb3_vbus-supply = <&reg_usb_vbus>;
 	status = "okay";
 };
+
+&usb3phy {
+	status = "okay";
+};

arch/arm/dts/sun5i-a13-ampe-a76.dts

@@ -26,3 +26,7 @@
 	pinctrl-0 = <&uart1_pg_pins>;
 	status = "okay";
 };
+
+&usbphy {
+	usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+};

arch/arm/dts/sun6i-a31-mixtile-loftq.dts

@@ -6,6 +6,9 @@
  */
 
 /dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
 #include "sun6i-a31.dtsi"
 
 / {
@@ -19,6 +22,15 @@
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	reg_usb1_vbus: usb1-vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb1-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */
+	};
 };
 
 &ehci0 {
@@ -56,3 +68,8 @@
 	pinctrl-0 = <&uart0_ph_pins>;
 	status = "okay";
 };
+
+&usbphy {
+	usb1_vbus-supply = <&reg_usb1_vbus>;
+	status = "okay";
+};

arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts

@@ -176,6 +176,7 @@
 };
 
 &usbphy {
+	usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
 	usb1_vbus-supply = <&reg_dldo1>;
 	usb2_vbus-supply = <&reg_dc1sw>;
 	status = "okay";

arch/arm/dts/sun8i-a33-inet-u70b-rev1.dts

@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+
+/dts-v1/;
+
+#include "sun8i-a33.dtsi"
+#include "sun8i-reference-design-tablet.dtsi"
+
+/ {
+	model = "iNet U70B REV01";
+	compatible = "inet-tek,inet-u70b-rev01", "allwinner,sun8i-a33";
+
+	aliases {
+		ethernet0 = &rtl8723cs;
+		serial0 = &uart0;
+	};
+
+	panel: panel {
+		compatible = "panel-dpi";
+		backlight = <&backlight>;
+		enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+		power-supply = <&reg_dc1sw>;
+
+		panel-timing {
+			clock-frequency = <51000000>;
+			hactive = <1024>;
+			vactive = <600>;
+			hfront-porch = <162>;
+			hback-porch = <158>;
+			hsync-len = <20>;
+			vback-porch = <25>;
+			vfront-porch = <10>;
+			vsync-len = <3>;
+			hsync-active = <1>;
+			vsync-active = <1>;
+		};
+
+		port {
+			panel_in_tcon0: endpoint {
+				remote-endpoint = <&tcon0_out_panel>;
+			};
+		};
+	};
+
+	speaker_amp: audio-amplifier {
+		compatible = "simple-audio-amplifier";
+		enable-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
+		sound-name-prefix = "Speaker Amp";
+	};
+
+	wifi_pwrseq: wifi-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */
+		post-power-on-delay-ms = <200>;
+	};
+};
+
+&codec {
+	status = "okay";
+};
+
+&dai {
+	status = "okay";
+};
+
+&de {
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+
+	accelerometer@18 {
+		compatible = "bosch,bma250";
+		reg = <0x18>;
+		interrupt-parent = <&pio>;
+		interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
+	};
+};
+
+&mmc0 {
+	status = "disabled";
+};
+
+&mmc1 {
+	pinctrl-0 = <&mmc1_pg_pins>;
+	pinctrl-names = "default";
+	bus-width = <4>;
+	non-removable;
+	vmmc-supply = <&reg_dldo1>;
+	vqmmc-supply = <&reg_dldo2>;
+	status = "okay";
+
+	rtl8723cs: wifi@1 {
+		reg = <1>;
+		interrupt-parent = <&r_pio>;
+		interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */
+	};
+};
+
+&nfc {
+	status = "okay";
+
+	nand@0 {
+		reg = <0>;
+		allwinner,rb = <0>;
+		nand-ecc-maximize;
+	};
+};
+
+&r_uart {
+	status = "disabled";
+};
+
+&reg_dldo2 {
+	regulator-min-microvolt = <3300000>;
+	regulator-max-microvolt = <3300000>;
+	regulator-name = "vcc-wifi-io";
+};
+
+&simplefb_lcd {
+	status = "okay";
+};
+
+&sound {
+	simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
+	simple-audio-card,widgets = "Headphone", "Headphone Jack",
+				    "Microphone", "Internal Microphone",
+				    "Speaker", "Internal Speaker";
+	simple-audio-card,routing = "Headphone Jack", "HP",
+				    "Internal Speaker", "Speaker Amp OUTL",
+				    "Internal Speaker", "Speaker Amp OUTR",
+				    "Speaker Amp INL", "HP", /* PHONEOUT ??? */
+				    "Speaker Amp INR", "HP", /* PHONEOUT ??? */
+				    "Left DAC", "DACL",
+				    "Right DAC", "DACR",
+				    "ADCL", "Left ADC",
+				    "ADCR", "Right ADC",
+				    "MIC1", "Internal Microphone",
+				    "MIC2", "Headset Microphone",
+				    "Headset Microphone", "HBIAS",
+				    "Internal Microphone", "MBIAS";
+	status = "okay";
+};
+
+&tcon0 {
+	pinctrl-0 = <&lcd_rgb666_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&tcon0_out {
+	tcon0_out_panel: endpoint {
+		remote-endpoint = <&panel_in_tcon0>;
+	};
+};
+
+&touchscreen {
+	reg = <0x40>;
+	compatible = "silead,gsl1680";
+	avdd-supply = <&reg_ldo_io1>;
+	touchscreen-size-x = <1024>;
+	touchscreen-size-y = <600>;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0_pf_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pg_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	bluetooth {
+		compatible = "realtek,rtl8723cs-bt";
+		device-wake-gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */
+		enable-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+		host-wake-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
+	};
+};

arch/arm/dts/sun8i-a33-sinlinx-sina33.dts

@@ -271,5 +271,6 @@
 
 &usbphy {
 	status = "okay";
+	usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
 	usb1_vbus-supply = <&reg_vcc5v0>; /* USB1 VBUS is always on */
 };

arch/arm/dts/sun8i-h3.dtsi

@@ -170,6 +170,14 @@
 			#size-cells = <1>;
 			ranges;
 
+			sram_a2: sram@40000 {
+				compatible = "mmio-sram";
+				reg = <0x00040000 0xc000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x00040000 0xc000>;
+			};
+
 			sram_c: sram@1d00000 {
 				compatible = "mmio-sram";
 				reg = <0x01d00000 0x80000>;
@@ -239,6 +247,12 @@
 			nvmem-cell-names = "calibration";
 			#thermal-sensor-cells = <0>;
 		};
+
+		remoteproc@1f01c00 {
+			compatible = "allwinner,sun6i-a31-ar100";
+			reg = <0x01f01c00 0x400>;
+			sram = <&sram_a2>;
+		};
 	};
 
 	thermal-zones {

arch/arm/dts/sun9i-a80-cubieboard4.dts

@@ -506,3 +506,7 @@
 	pinctrl-0 = <&uart0_ph_pins>;
 	status = "okay";
 };
+
+&usbphy {
+	usb0_id_det-gpios = <&pio 7 16 GPIO_ACTIVE_HIGH>; /* PH16 */
+};

arch/arm/dts/sunxi-u-boot.dtsi

@@ -1,13 +1,24 @@
 #include <config.h>
 
-#ifdef CONFIG_MACH_SUN50I_H6
+#ifdef CONFIG_ARM64
-#define BL31_ADDR 0x104000
+#define ARCH "arm64"
-#define  SCP_ADDR 0x114000
+#else
+#define ARCH "arm"
+#endif
+
+#if defined(CONFIG_MACH_SUN8I_H3)
+#ifdef CONFIG_ARMV7_PSCI
+#define RESUME_ADDR	SUNXI_RESUME_BASE
+#define SCP_ADDR	SUNXI_SCP_BASE
+#endif
+#elif defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H5)
+#define BL31_ADDR	0x00044000
+#define SCP_ADDR	0x00050000
+#elif defined(CONFIG_MACH_SUN50I_H6)
+#define BL31_ADDR	0x00104000
+#define SCP_ADDR	0x00114000
 #elif defined(CONFIG_MACH_SUN50I_H616)
 #define BL31_ADDR	0x40000000
-#else
-#define BL31_ADDR  0x44000
-#define  SCP_ADDR  0x50000
 #endif
 
 / {
@@ -34,30 +45,33 @@
 			filename = "spl/sunxi-spl.bin";
 		};
 
-#ifdef CONFIG_ARM64
+#ifdef CONFIG_SPL_LOAD_FIT
 		fit {
-			description = "Configuration to load ATF before U-Boot";
+			description = "Configuration to load U-Boot and firmware";
+			offset = <32768>;
 			#address-cells = <1>;
 			fit,fdt-list = "of-list";
 
 			images {
 				uboot {
-					description = "U-Boot (64-bit)";
+					description = "U-Boot";
 					type = "standalone";
 					os = "u-boot";
-					arch = "arm64";
+					arch = ARCH;
 					compression = "none";
 					load = <CONFIG_SYS_TEXT_BASE>;
+					entry = <CONFIG_SYS_TEXT_BASE>;
 
 					u-boot-nodtb {
 					};
 				};
 
+#ifdef BL31_ADDR
 				atf {
 					description = "ARM Trusted Firmware";
 					type = "firmware";
 					os = "arm-trusted-firmware";
-					arch = "arm64";
+					arch = ARCH;
 					compression = "none";
 					load = <BL31_ADDR>;
 					entry = <BL31_ADDR>;
@@ -67,6 +81,21 @@
 						missing-msg = "atf-bl31-sunxi";
 					};
 				};
+#endif
+
+#ifdef RESUME_ADDR
+				resume {
+					description = "Super Standby resume image";
+					type = "standalone";
+					arch = ARCH;
+					compression = "none";
+					load = <RESUME_ADDR>;
+
+					blob-ext {
+						filename = "u-boot-resume.img";
+					};
+				};
+#endif
 
 #ifdef SCP_ADDR
 				scp {
@@ -95,19 +124,26 @@
 
 				@config-SEQ {
 					description = "NAME";
+#ifdef BL31_ADDR
 					firmware = "atf";
-#ifndef SCP_ADDR
-					loadables = "uboot";
 #else
-					loadables = "scp", "uboot";
+					firmware = "uboot";
 #endif
+					loadables =
+#ifdef RESUME_ADDR
+						    "resume",
+#endif
+#ifdef SCP_ADDR
+						    "scp",
+#endif
+						    "uboot";
 					fdt = "fdt-SEQ";
 				};
 			};
 		};
 #else
 		u-boot-img {
-			offset = <CONFIG_SPL_PAD_TO>;
+			offset = <32768>;
 		};
 #endif
 	};

arch/arm/include/asm/arch-sunxi/gpio.h

@@ -9,7 +9,9 @@
 #define _SUNXI_GPIO_H
 
 #include <linux/types.h>
+#if 0
 #include <asm/arch/cpu.h>
+#endif
 
 /*
  * sunxi has 9 banks of gpio, they are:
@@ -55,30 +57,36 @@
 struct sunxi_gpio {
 	u32 cfg[4];
 	u32 dat;
-	u32 drv[2];
+	u32 drv[4];
 	u32 pull[2];
+	u32 reserved;
 };
 
 /* gpio interrupt control */
 struct sunxi_gpio_int {
-	u32 cfg[3];
+	u32 cfg[4];
 	u32 ctl;
 	u32 sta;
 	u32 deb;		/* interrupt debounce */
+	u32 reserved;
 };
 
+#if 0
 struct sunxi_gpio_reg {
 	struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS];
 	u8 res[0xbc];
 	struct sunxi_gpio_int gpio_int;
 };
+#endif
 
 #define SUN50I_H6_GPIO_POW_MOD_SEL	0x340
 #define SUN50I_H6_GPIO_POW_MOD_VAL	0x348
 
+#if 0
 #define BANK_TO_GPIO(bank)	(((bank) < SUNXI_GPIO_L) ? \
 	&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
 	&((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L])
+#endif
 
 #define GPIO_BANK(pin)		((pin) >> 5)
 #define GPIO_NUM(pin)		((pin) & 0x1f)
@@ -111,7 +119,6 @@ enum sunxi_gpio_number {
 	SUNXI_GPIO_L_START = 352,
 	SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
 	SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
-	SUNXI_GPIO_AXP0_START = 1024,
 };
 
 /* SUNXI GPIO number definitions */
@@ -128,8 +135,6 @@ enum sunxi_gpio_number {
 #define SUNXI_GPM(_nr)	(SUNXI_GPIO_M_START + (_nr))
 #define SUNXI_GPN(_nr)	(SUNXI_GPIO_N_START + (_nr))
 
-#define SUNXI_GPAXP0(_nr)	(SUNXI_GPIO_AXP0_START + (_nr))
-
 /* GPIO pin function config */
 #define SUNXI_GPIO_INPUT	0
 #define SUNXI_GPIO_OUTPUT	1
@@ -207,12 +212,6 @@ enum sunxi_gpio_number {
 #define SUNXI_GPIO_PULL_UP	1
 #define SUNXI_GPIO_PULL_DOWN	2
 
-/* Virtual AXP0 GPIOs */
-#define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
-#define SUNXI_GPIO_AXP0_VBUS_DETECT	4
-#define SUNXI_GPIO_AXP0_VBUS_ENABLE	5
-#define SUNXI_GPIO_AXP0_GPIO_COUNT	6
-
 struct sunxi_gpio_plat {
 	struct sunxi_gpio	*regs;
 	char			bank_name[3];
@@ -228,10 +227,4 @@ void sunxi_gpio_set_pull(u32 pin, u32 val);
 void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val);
 int sunxi_name_to_gpio(const char *name);
 
-#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
-int axp_gpio_init(void);
-#else
-static inline int axp_gpio_init(void) { return 0; }
-#endif
-
 #endif /* _SUNXI_GPIO_H */

arch/arm/include/asm/arch-sunxi/i2c.h

@@ -17,7 +17,4 @@
 #define CONFIG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE
 #endif
 
-/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
-#define CONFIG_SYS_TCLK		24000000
-
 #endif

arch/arm/include/asm/arch-sunxi/mmc.h

@@ -1,139 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2007-2011
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Aaron <leafy.myeh@allwinnertech.com>
- *
- * MMC register definition for allwinner sunxi platform.
- */
 
-#ifndef _SUNXI_MMC_H
+#ifndef _ARCH_SUNXI_MMC_H
-#define _SUNXI_MMC_H
+#define _ARCH_SUNXI_MMC_H
-
-#include <linux/types.h>
-
-struct sunxi_mmc {
-	u32 gctrl;		/* 0x00 global control */
-	u32 clkcr;		/* 0x04 clock control */
-	u32 timeout;		/* 0x08 time out */
-	u32 width;		/* 0x0c bus width */
-	u32 blksz;		/* 0x10 block size */
-	u32 bytecnt;		/* 0x14 byte count */
-	u32 cmd;		/* 0x18 command */
-	u32 arg;		/* 0x1c argument */
-	u32 resp0;		/* 0x20 response 0 */
-	u32 resp1;		/* 0x24 response 1 */
-	u32 resp2;		/* 0x28 response 2 */
-	u32 resp3;		/* 0x2c response 3 */
-	u32 imask;		/* 0x30 interrupt mask */
-	u32 mint;		/* 0x34 masked interrupt status */
-	u32 rint;		/* 0x38 raw interrupt status */
-	u32 status;		/* 0x3c status */
-	u32 ftrglevel;		/* 0x40 FIFO threshold watermark*/
-	u32 funcsel;		/* 0x44 function select */
-	u32 cbcr;		/* 0x48 CIU byte count */
-	u32 bbcr;		/* 0x4c BIU byte count */
-	u32 dbgc;		/* 0x50 debug enable */
-	u32 res0;		/* 0x54 reserved */
-	u32 a12a;		/* 0x58 Auto command 12 argument */
-	u32 ntsr;		/* 0x5c	New timing set register */
-	u32 res1[8];
-	u32 dmac;		/* 0x80 internal DMA control */
-	u32 dlba;		/* 0x84 internal DMA descr list base address */
-	u32 idst;		/* 0x88 internal DMA status */
-	u32 idie;		/* 0x8c internal DMA interrupt enable */
-	u32 chda;		/* 0x90 */
-	u32 cbda;		/* 0x94 */
-	u32 res2[26];
-#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
-	u32 res3[17];
-	u32 samp_dl;
-	u32 res4[46];
-#endif
-	u32 fifo;		/* 0x100 / 0x200 FIFO access address */
-};
-
-#define SUNXI_MMC_CLK_POWERSAVE		(0x1 << 17)
-#define SUNXI_MMC_CLK_ENABLE		(0x1 << 16)
-#define SUNXI_MMC_CLK_DIVIDER_MASK	(0xff)
-
-#define SUNXI_MMC_GCTRL_SOFT_RESET	(0x1 << 0)
-#define SUNXI_MMC_GCTRL_FIFO_RESET	(0x1 << 1)
-#define SUNXI_MMC_GCTRL_DMA_RESET	(0x1 << 2)
-#define SUNXI_MMC_GCTRL_RESET		(SUNXI_MMC_GCTRL_SOFT_RESET|\
-					 SUNXI_MMC_GCTRL_FIFO_RESET|\
-					 SUNXI_MMC_GCTRL_DMA_RESET)
-#define SUNXI_MMC_GCTRL_DMA_ENABLE	(0x1 << 5)
-#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB   (0x1 << 31)
-
-#define SUNXI_MMC_CMD_RESP_EXPIRE	(0x1 << 6)
-#define SUNXI_MMC_CMD_LONG_RESPONSE	(0x1 << 7)
-#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC	(0x1 << 8)
-#define SUNXI_MMC_CMD_DATA_EXPIRE	(0x1 << 9)
-#define SUNXI_MMC_CMD_WRITE		(0x1 << 10)
-#define SUNXI_MMC_CMD_AUTO_STOP		(0x1 << 12)
-#define SUNXI_MMC_CMD_WAIT_PRE_OVER	(0x1 << 13)
-#define SUNXI_MMC_CMD_SEND_INIT_SEQ	(0x1 << 15)
-#define SUNXI_MMC_CMD_UPCLK_ONLY	(0x1 << 21)
-#define SUNXI_MMC_CMD_START		(0x1 << 31)
-
-#define SUNXI_MMC_RINT_RESP_ERROR		(0x1 << 1)
-#define SUNXI_MMC_RINT_COMMAND_DONE		(0x1 << 2)
-#define SUNXI_MMC_RINT_DATA_OVER		(0x1 << 3)
-#define SUNXI_MMC_RINT_TX_DATA_REQUEST		(0x1 << 4)
-#define SUNXI_MMC_RINT_RX_DATA_REQUEST		(0x1 << 5)
-#define SUNXI_MMC_RINT_RESP_CRC_ERROR		(0x1 << 6)
-#define SUNXI_MMC_RINT_DATA_CRC_ERROR		(0x1 << 7)
-#define SUNXI_MMC_RINT_RESP_TIMEOUT		(0x1 << 8)
-#define SUNXI_MMC_RINT_DATA_TIMEOUT		(0x1 << 9)
-#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE	(0x1 << 10)
-#define SUNXI_MMC_RINT_FIFO_RUN_ERROR		(0x1 << 11)
-#define SUNXI_MMC_RINT_HARD_WARE_LOCKED		(0x1 << 12)
-#define SUNXI_MMC_RINT_START_BIT_ERROR		(0x1 << 13)
-#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE	(0x1 << 14)
-#define SUNXI_MMC_RINT_END_BIT_ERROR		(0x1 << 15)
-#define SUNXI_MMC_RINT_SDIO_INTERRUPT		(0x1 << 16)
-#define SUNXI_MMC_RINT_CARD_INSERT		(0x1 << 30)
-#define SUNXI_MMC_RINT_CARD_REMOVE		(0x1 << 31)
-#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT      \
-	(SUNXI_MMC_RINT_RESP_ERROR |		\
-	 SUNXI_MMC_RINT_RESP_CRC_ERROR |	\
-	 SUNXI_MMC_RINT_DATA_CRC_ERROR |	\
-	 SUNXI_MMC_RINT_RESP_TIMEOUT |		\
-	 SUNXI_MMC_RINT_DATA_TIMEOUT |		\
-	 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE |	\
-	 SUNXI_MMC_RINT_FIFO_RUN_ERROR |	\
-	 SUNXI_MMC_RINT_HARD_WARE_LOCKED |	\
-	 SUNXI_MMC_RINT_START_BIT_ERROR |	\
-	 SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
-#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT	\
-	(SUNXI_MMC_RINT_AUTO_COMMAND_DONE |	\
-	 SUNXI_MMC_RINT_DATA_OVER |		\
-	 SUNXI_MMC_RINT_COMMAND_DONE |		\
-	 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
-
-#define SUNXI_MMC_STATUS_RXWL_FLAG		(0x1 << 0)
-#define SUNXI_MMC_STATUS_TXWL_FLAG		(0x1 << 1)
-#define SUNXI_MMC_STATUS_FIFO_EMPTY		(0x1 << 2)
-#define SUNXI_MMC_STATUS_FIFO_FULL		(0x1 << 3)
-#define SUNXI_MMC_STATUS_CARD_PRESENT		(0x1 << 8)
-#define SUNXI_MMC_STATUS_CARD_DATA_BUSY		(0x1 << 9)
-#define SUNXI_MMC_STATUS_DATA_FSM_BUSY		(0x1 << 10)
-#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg)	(((reg) >> 17) & 0x3fff)
-
-#define SUNXI_MMC_NTSR_MODE_SEL_NEW		(0x1 << 31)
-
-#define SUNXI_MMC_IDMAC_RESET		(0x1 << 0)
-#define SUNXI_MMC_IDMAC_FIXBURST	(0x1 << 1)
-#define SUNXI_MMC_IDMAC_ENABLE		(0x1 << 7)
-
-#define SUNXI_MMC_IDIE_TXIRQ		(0x1 << 0)
-#define SUNXI_MMC_IDIE_RXIRQ		(0x1 << 1)
-
-#define SUNXI_MMC_COMMON_CLK_GATE		(1 << 16)
-#define SUNXI_MMC_COMMON_RESET			(1 << 18)
-
-#define SUNXI_MMC_CAL_DL_SW_EN		(0x1 << 7)
 
 struct mmc *sunxi_mmc_init(int sdc_no);
-#endif /* _SUNXI_MMC_H */
+
+#endif /* _ARCH_SUNXI_MMC_H */

arch/arm/include/asm/psci.h

@@ -22,8 +22,9 @@
 #include <linux/bitops.h>
 #endif
 
-#define ARM_PSCI_VER_1_0		(0x00010000)
 #define ARM_PSCI_VER_0_2		(0x00000002)
+#define ARM_PSCI_VER_1_0		(0x00010000)
+#define ARM_PSCI_VER_1_1		(0x00010001)
 
 /* PSCI 0.1 interface */
 #define ARM_PSCI_FN_BASE		0x95c1ba5e
@@ -68,7 +69,6 @@
 #define ARM_PSCI_0_2_FN64_AFFINITY_INFO		ARM_PSCI_0_2_FN64(4)
 #define ARM_PSCI_0_2_FN64_MIGRATE		ARM_PSCI_0_2_FN64(5)
 #define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU	ARM_PSCI_0_2_FN64(7)
-#define ARM_PSCI_0_2_FN64_SYSTEM_RESET2		ARM_PSCI_0_2_FN64(18)
 
 /* PSCI 1.0 interface */
 #define ARM_PSCI_1_0_FN_PSCI_FEATURES		ARM_PSCI_0_2_FN(10)
@@ -86,6 +86,11 @@
 #define ARM_PSCI_1_0_FN64_STAT_RESIDENCY	ARM_PSCI_0_2_FN64(16)
 #define ARM_PSCI_1_0_FN64_STAT_COUNT		ARM_PSCI_0_2_FN64(17)
 
+/* PSCI 1.1 interface */
+#define ARM_PSCI_1_1_FN_SYSTEM_RESET2		ARM_PSCI_0_2_FN(18)
+
+#define ARM_PSCI_1_1_FN64_SYSTEM_RESET2		ARM_PSCI_0_2_FN64(18)
+
 /* 1KB stack per core */
 #define ARM_PSCI_STACK_SHIFT	10
 #define ARM_PSCI_STACK_SIZE	(1 << ARM_PSCI_STACK_SHIFT)

arch/arm/include/asm/system.h

@@ -557,16 +557,20 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop);
 #ifdef CONFIG_ARMV7_PSCI
 void psci_arch_cpu_entry(void);
 void psci_arch_init(void);
+
 u32 psci_version(void);
-s32 psci_features(u32 function_id, u32 psci_fid);
+s32 psci_cpu_suspend(u32 function_id, u32 power_state, u32 pc, u32 context_id);
 s32 psci_cpu_off(void);
-s32 psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
+s32 psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc, u32 context_id);
-		u32 context_id);
+s32 psci_affinity_info(u32 function_id, u32 target_affinity, u32 power_level);
-s32 psci_affinity_info(u32 function_id, u32 target_affinity,
-		       u32  lowest_affinity_level);
 u32 psci_migrate_info_type(void);
 void psci_system_off(void);
 void psci_system_reset(void);
+s32 psci_features(u32 function_id, u32 psci_fid);
+s32 psci_cpu_default_suspend(u32 function_id, u32 pc, u32 context_id);
+s32 psci_node_hw_state(u32 function_id, u32 target_cpu, u32 power_level);
+s32 psci_system_suspend(u32 function_id, u32 pc, u32 context_id);
+s32 psci_system_reset2(u32 function_id, u32 reset_type, u32 cookie);
 #endif
 
 #endif /* __ASSEMBLY__ */

arch/arm/lib/psci-dt.c

@@ -66,6 +66,8 @@ int fdt_psci(void *fdt)
 init_psci_node:
 #if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT)
 	psci_ver = sec_firmware_support_psci_version();
+#elif defined(CONFIG_ARMV7_PSCI_1_1)
+	psci_ver = ARM_PSCI_VER_1_1;
 #elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI)
 	psci_ver = ARM_PSCI_VER_1_0;
 #elif defined(CONFIG_ARMV7_PSCI_0_2)

arch/arm/mach-sunxi/Kconfig

@@ -683,58 +683,6 @@ config MMC_SUNXI_SLOT_EXTRA
 	slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
 	support for this.
 
-config INITIAL_USB_SCAN_DELAY
-	int "delay initial usb scan by x ms to allow builtin devices to init"
-	default 0
-	---help---
-	Some boards have on board usb devices which need longer than the
-	USB spec's 1 second to connect from board powerup. Set this config
-	option to a non 0 value to add an extra delay before the first usb
-	bus scan.
-
-config USB0_VBUS_PIN
-	string "Vbus enable pin for usb0 (otg)"
-	default ""
-	---help---
-	Set the Vbus enable pin for usb0 (otg). This takes a string in the
-	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config USB0_VBUS_DET
-	string "Vbus detect pin for usb0 (otg)"
-	default ""
-	---help---
-	Set the Vbus detect pin for usb0 (otg). This takes a string in the
-	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config USB0_ID_DET
-	string "ID detect pin for usb0 (otg)"
-	default ""
-	---help---
-	Set the ID detect pin for usb0 (otg). This takes a string in the
-	format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
-
-config USB1_VBUS_PIN
-	string "Vbus enable pin for usb1 (ehci0)"
-	default "PH6" if MACH_SUN4I || MACH_SUN7I
-	default "PH27" if MACH_SUN6I
-	---help---
-	Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
-	a string in the format understood by sunxi_name_to_gpio, e.g.
-	PH1 for pin 1 of port H.
-
-config USB2_VBUS_PIN
-	string "Vbus enable pin for usb2 (ehci1)"
-	default "PH3" if MACH_SUN4I || MACH_SUN7I
-	default "PH24" if MACH_SUN6I
-	---help---
-	See USB1_VBUS_PIN help text.
-
-config USB3_VBUS_PIN
-	string "Vbus enable pin for usb3 (ehci2)"
-	default ""
-	---help---
-	See USB1_VBUS_PIN help text.
-
 config I2C0_ENABLE
 	bool "Enable I2C/TWI controller 0"
 	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
@@ -762,12 +710,6 @@ config R_I2C_ENABLE
 	Set this to y to enable the I2C controller which is part of the PRCM.
 endif
 
-config AXP_GPIO
-	bool "Enable support for gpio-s on axp PMICs"
-	depends on AXP_PMIC_BUS
-	---help---
-	Say Y here to enable support for the gpio pins of the axp PMIC ICs.
-
 config AXP_DISABLE_BOOT_ON_POWERON
 	bool "Disable device boot on power plug-in"
 	depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
@@ -1044,8 +986,6 @@ config BLUETOOTH_DT_DEVICE_FIXUP
 	  The used address is "bdaddr" if set, and "ethaddr" with the LSB
 	  flipped elsewise.
 
-source "board/sunxi/Kconfig"
-
 endif
 
 config CHIP_DIP_SCAN

arch/arm/mach-sunxi/pinmux.c

@@ -7,7 +7,7 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/gpio.h>
+//#include <asm/arch/gpio.h>
 
 void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
 {
@@ -17,6 +17,7 @@ void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
 	clrsetbits_le32(&pio->cfg[index], 0xf << offset, val << offset);
 }
 
+#if !CONFIG_IS_ENABLED(DM_GPIO)
 void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
 {
 	u32 bank = GPIO_BANK(pin);
@@ -24,6 +25,7 @@ void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
 
 	sunxi_gpio_set_cfgbank(pio, pin, val);
 }
+#endif
 
 int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
 {
@@ -37,6 +39,7 @@ int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
 	return cfg & 0xf;
 }
 
+#if !CONFIG_IS_ENABLED(DM_GPIO)
 int sunxi_gpio_get_cfgpin(u32 pin)
 {
 	u32 bank = GPIO_BANK(pin);
@@ -52,6 +55,7 @@ void sunxi_gpio_set_drv(u32 pin, u32 val)
 
 	sunxi_gpio_set_drv_bank(pio, pin, val);
 }
+#endif
 
 void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val)
 {
@@ -61,6 +65,7 @@ void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val)
 	clrsetbits_le32(&pio->drv[index], 0x3 << offset, val << offset);
 }
 
+#if !CONFIG_IS_ENABLED(DM_GPIO)
 void sunxi_gpio_set_pull(u32 pin, u32 val)
 {
 	u32 bank = GPIO_BANK(pin);
@@ -68,6 +73,7 @@ void sunxi_gpio_set_pull(u32 pin, u32 val)
 
 	sunxi_gpio_set_pull_bank(pio, pin, val);
 }
+#endif
 
 void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val)
 {

arch/riscv/Kconfig

@@ -14,6 +14,9 @@ config TARGET_AX25_AE350
 config TARGET_MICROCHIP_ICICLE
 	bool "Support Microchip PolarFire-SoC Icicle Board"
 
+config TARGET_OPENPITON_RISCV64
+	bool "Support RISC-V cores on OpenPiton SoC"
+
 config TARGET_QEMU_VIRT
 	bool "Support QEMU Virt Board"
 
@@ -28,8 +31,9 @@ config TARGET_SIPEED_MAIX
 	bool "Support Sipeed Maix Board"
 	select SYS_CACHE_SHIFT_6
 
-config TARGET_OPENPITON_RISCV64
+config TARGET_SUNXI
-	bool "Support RISC-V cores on OpenPiton SoC"
+	bool "Support Allwinner sunxi SoCs with RISC-V cores"
+	select SYS_CACHE_SHIFT_6
 
 endchoice
 
@@ -61,9 +65,9 @@ config SPL_SYS_DCACHE_OFF
 source "board/AndesTech/ax25-ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
 source "board/microchip/mpfs_icicle/Kconfig"
+source "board/openpiton/riscv64/Kconfig"
 source "board/sifive/unleashed/Kconfig"
 source "board/sifive/unmatched/Kconfig"
-source "board/openpiton/riscv64/Kconfig"
 source "board/sipeed/maix/Kconfig"
 
 # platform-specific options below

arch/riscv/cpu/Makefile

@@ -5,3 +5,4 @@
 extra-y = start.o
 
 obj-y += cpu.o mtrap.o
+obj-y += thead/cache.o

arch/riscv/cpu/thead/cache.c

@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <asm/cache.h>
+#include <asm/csr.h>
+
+#define CSR_MHCR		0x7c1
+#define CSR_MCOR		0x7c2
+#define CSR_MHINT		0x7c5
+
+#define MHCR_IE			BIT(0)	/* icache enable */
+#define MHCR_DE			BIT(1)	/* dcache enable */
+#define MHCR_WA			BIT(2)	/* dcache write allocate */
+#define MHCR_WB			BIT(3)	/* dcache write back */
+#define MHCR_RS			BIT(4)	/* return stack enable */
+#define MHCR_BPE		BIT(5)	/* branch prediction enable */
+#define MHCR_BTB		BIT(6)	/* branch target prediction enable */
+#define MHCR_WBR		BIT(8)	/* write burst enable */
+#define MHCR_L0BTB		BIT(12)
+
+#define MCOR_CACHE_SEL_ICACHE	(0x1 << 0)
+#define MCOR_CACHE_SEL_DCACHE	(0x2 << 0)
+#define MCOR_CACHE_SEL_BOTH	(0x3 << 0)
+#define MCOR_INV		BIT(4)
+#define MCOR_CLR		BIT(5)
+#define MCOR_BHT_INV		BIT(16)
+#define MCOR_BTB_INV		BIT(17)
+
+#define MHINT_DPLD		BIT(2)	/* dcache prefetch enable */
+#define MHINT_AMR_PAGE		(0x0 << 3)
+#define MHINT_AMR_LIMIT_3	(0x1 << 3)
+#define MHINT_AMR_LIMIT_64	(0x2 << 3)
+#define MHINT_AMR_LIMIT_128	(0x3 << 3)
+#define MHINT_IPLD		BIT(8)	/* icache prefetch enable */
+#define MHINT_IWPE		BIT(9)	/* icache prediction enable */
+#define MHINT_DIS_PREFETCH_2	(0x0 << 13)
+#define MHINT_DIS_PREFETCH_4	(0x1 << 13)
+#define MHINT_DIS_PREFETCH_8	(0x2 << 13)
+#define MHINT_DIS_PREFETCH_16	(0x3 << 13)
+
+#define sync_i()		asm volatile (".long 0x01a0000b" ::: "memory")
+
+void flush_dcache_all(void)
+{
+	asm volatile (".long 0x0030000b" ::: "memory"); /* dcache.ciall */
+	sync_i();
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+	register unsigned long i asm("a0") = start & -CONFIG_SYS_CACHELINE_SIZE;
+
+	for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
+		asm volatile (".long 0x02b5000b" ::: "memory"); /* dcache.cipa a0 */
+	sync_i();
+}
+
+void invalidate_icache_range(unsigned long start, unsigned long end)
+{
+	register unsigned long i asm("a0") = start & -CONFIG_SYS_CACHELINE_SIZE;
+
+	for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
+		asm volatile (".long 0x0385000b" ::: "memory"); /* icache.ipa a0 */
+	sync_i();
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+	register unsigned long i asm("a0") = start & -CONFIG_SYS_CACHELINE_SIZE;
+
+	for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
+		asm volatile (".long 0x02a5000b" ::: "memory"); /* dcache.ipa a0 */
+	sync_i();
+}
+
+#if 0
+void icache_enable(void)
+{
+	asm volatile (".long 0x0100000b" ::: "memory"); /* icache.iall */
+	sync_i();
+	csr_set(CSR_MHCR, MHCR_IE | MHCR_RS | MHCR_BPE | MHCR_BTB | MHCR_L0BTB);
+	csr_set(CSR_MHINT, MHINT_IPLD | MHINT_IWPE);
+}
+
+void icache_disable(void)
+{
+	csr_clear(CSR_MHCR, MHCR_IE);
+}
+
+int icache_status(void)
+{
+	return csr_read(CSR_MHCR) & MHCR_IE;
+}
+
+void dcache_enable(void)
+{
+	asm volatile (".long 0x0020000b" ::: "memory"); /* dcache.iall */
+	sync_i();
+	csr_set(CSR_MHCR, MHCR_DE | MHCR_WA | MHCR_WB | MHCR_WBR);
+	csr_set(CSR_MHINT, MHINT_DPLD | MHINT_AMR_LIMIT_3);
+}
+
+void dcache_disable(void)
+{
+	asm volatile (".long 0x0010000b" ::: "memory"); /* dcache.call */
+	sync_i();
+	csr_clear(CSR_MHCR, MHCR_DE);
+}
+
+int dcache_status(void)
+{
+	return csr_read(CSR_MHCR) & MHCR_DE;
+}
+
+void enable_caches(void)
+{
+	icache_enable();
+	dcache_enable();
+}
+#endif

arch/riscv/dts/Makefile

@@ -7,6 +7,11 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
+dtb-$(CONFIG_TARGET_SUNXI) += \
+	sun20i-d1-lichee-rv.dtb \
+	sun20i-d1-lichee-rv-86-panel.dtb \
+	sun20i-d1-lichee-rv-dock.dtb \
+	sun20i-d1-nezha.dtb
 
 include $(srctree)/scripts/Makefile.dts
 

arch/riscv/dts/sun20i-d1-common-regulators.dtsi

@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
+
+/ {
+	reg_vcc: vcc {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	reg_vcc_3v3: vcc-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&reg_vcc>;
+	};
+};
+
+&codec {
+	avcc-supply = <&reg_aldo>;
+	hpvcc-supply = <&reg_hpldo>;
+	vdd33-supply = <&reg_vcc_3v3>;
+};
+
+&gpio {
+	vcc-pb-supply = <&reg_vcc_3v3>;
+	vcc-pc-supply = <&reg_vcc_3v3>;
+	vcc-pd-supply = <&reg_vcc_3v3>;
+	vcc-pe-supply = <&reg_vcc_3v3>;
+	vcc-pf-supply = <&reg_vcc_3v3>;
+	vcc-pg-supply = <&reg_vcc_3v3>;
+};
+
+&hdmi {
+	hvcc-supply = <&reg_ldoa>;
+};
+
+&lradc {
+	vref-supply = <&reg_aldo>;
+};
+
+&reg_aldo {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	vdd33-supply = <&reg_vcc_3v3>;
+};
+
+&reg_hpldo {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	hpldoin-supply = <&reg_vcc_3v3>;
+};
+
+&reg_ldoa {
+	regulator-always-on;
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	ldo-in-supply = <&reg_vcc_3v3>;
+};
+
+&ths {
+	vref-supply = <&reg_aldo>;
+};

arch/riscv/dts/sun20i-d1-lichee-rv-86-panel.dts

@@ -0,0 +1,240 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
+
+#include <dt-bindings/input/input.h>
+
+#include "sun20i-d1-lichee-rv.dts"
+
+/ {
+	model = "Sipeed Lichee RV 86 Panel";
+	compatible = "sipeed,lichee-rv-86-panel", "sipeed,lichee-rv",
+		     "allwinner,sun20i-d1";
+
+	aliases {
+		ethernet0 = &emac;
+		mmc1 = &mmc1;
+		serial3 = &uart3;
+	};
+
+	amplifier: audio-amplifier {
+		compatible = "simple-audio-amplifier";
+		enable-gpios = <&gpio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */
+		sound-name-prefix = "Amplifier";
+	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		power-supply = <&reg_vcc>;
+		pwms = <&pwm 7 50000 0>;
+	};
+
+	dmic-card {
+		compatible = "simple-audio-card";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		simple-audio-card,dai-link@0 {
+			format = "pdm";
+			frame-master = <&link0_cpu>;
+			bitclock-master = <&link0_cpu>;
+
+			link0_cpu: cpu {
+				sound-dai = <&dmic>;
+			};
+
+			link0_codec: codec {
+				sound-dai = <&dmic_codec>;
+			};
+		};
+	};
+
+	dmic_codec: dmic-codec {
+		compatible = "dmic-codec";
+		num-channels = <1>;
+		#sound-dai-cells = <0>;
+	};
+
+	spi-gpio {
+		compatible = "spi-gpio";
+		cs-gpios = <&gpio 4 14 GPIO_ACTIVE_LOW>; /* PE14 */
+		mosi-gpios = <&gpio 4 12 GPIO_ACTIVE_HIGH>; /* PE12 */
+		sck-gpios = <&gpio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */
+		num-chipselects = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		panel@0 {
+			compatible = "sitronix,st7701s";
+			reg = <0>;
+			backlight = <&backlight>;
+			reset-gpios = <&gpio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */
+			spi-3wire;
+
+			port {
+				panel_in_tcon_lcd0: endpoint {
+					remote-endpoint = <&tcon_lcd0_out_panel>;
+				};
+			};
+		};
+	};
+
+	wifi_pwrseq: wifi-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&ccu CLK_FANOUT1>;
+		clock-names = "ext_clock";
+		reset-gpios = <&gpio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
+		assigned-clocks = <&ccu CLK_FANOUT1>;
+		assigned-clock-rates = <32768>;
+		pinctrl-0 = <&clk_pg11_pin>;
+		pinctrl-names = "default";
+	};
+};
+
+&codec {
+	allwinner,aux-devs = <&amplifier>;
+	allwinner,routing = "Internal Speaker", "Amplifier OUTL",
+			    "Internal Speaker", "Amplifier OUTR",
+			    "Amplifier INL", "HPOUTL",
+			    "Amplifier INR", "HPOUTR",
+			    "LINEINL", "HPOUTL",
+			    "LINEINR", "HPOUTR",
+			    "MICIN3", "Internal Microphone",
+			    "Internal Microphone", "HBIAS";
+	allwinner,widgets = "Microphone", "Internal Microphone",
+			    "Speaker", "Internal Speaker";
+	status = "okay";
+};
+
+&de {
+	status = "okay";
+};
+
+&dmic {
+	pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&emac {
+	pinctrl-0 = <&rmii_pe_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&ext_rmii_phy>;
+	phy-mode = "rmii";
+	phy-supply = <&reg_vcc_3v3>;
+	status = "okay";
+};
+
+&gpio {
+	clk_pg11_pin: clk-pg11-pin {
+		pins = "PG11";
+		function = "clk";
+	};
+
+	dmic_pb11_d0_pin: dmic-pb11-d0-pin {
+		pins = "PB11";
+		function = "dmic";
+	};
+
+	dmic_pe17_clk_pin: dmic-pe17-clk-pin {
+		pins = "PE17";
+		function = "dmic";
+	};
+
+	pwm7_pd22_pin: pwm7-pd22-pin {
+		pins = "PD22";
+		function = "pwm";
+	};
+
+	uart3_pb_pins: uart3-pb-pins {
+		pins = "PB6", "PB7";
+		function = "uart3";
+	};
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_pb0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	touchscreen@48 {
+		compatible = "focaltech,ft6336u", "focaltech,ft6236";
+		reg = <0x48>;
+		interrupt-parent = <&gpio>;
+		interrupts = <6 14 IRQ_TYPE_LEVEL_LOW>; /* PG14 */
+		reset-gpios = <&gpio 6 15 GPIO_ACTIVE_LOW>; /* PG15 */
+		wakeup-source;
+		vcc-supply = <&reg_vcc_3v3>;
+		iovcc-supply = <&reg_vcc_3v3>;
+		touchscreen-size-x = <480>;
+		touchscreen-size-y = <480>;
+	};
+};
+
+&mdio {
+	ext_rmii_phy: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+		reset-gpios = <&gpio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
+	};
+};
+
+&mmc1 {
+	bus-width = <4>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	non-removable;
+	vmmc-supply = <&reg_vcc_3v3>;
+	vqmmc-supply = <&reg_vcc_3v3>;
+	pinctrl-0 = <&mmc1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&pwm {
+	pinctrl-0 = <&pwm7_pd22_pin>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&tcon_lcd0 {
+	pinctrl-0 = <&lcd_rgb666_pins>;
+	pinctrl-names = "default";
+};
+
+&tcon_lcd0_out {
+	tcon_lcd0_out_panel: endpoint {
+		remote-endpoint = <&panel_in_tcon_lcd0>;
+	};
+};
+
+&uart1 {
+	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	bluetooth {
+		compatible = "xradio,xr829-bt";
+		interrupt-parent = <&gpio>;
+		interrupts = <2 0 IRQ_TYPE_LEVEL_LOW>; /* PC0 */
+		device-wakeup-gpios = <&gpio 2 1 GPIO_ACTIVE_LOW>; /* PC1 */
+		reset-gpios = <&gpio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
+	};
+};
+
+&uart3 {
+	pinctrl-0 = <&uart3_pb_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usbphy {
+	/delete-property/ usb0_vbus_det-gpios;
+	usb1_vbus-supply = <&reg_vcc>;
+};

arch/riscv/dts/sun20i-d1-lichee-rv-dock.dts

@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
+
+#include <dt-bindings/input/input.h>
+
+#include "sun20i-d1-lichee-rv.dts"
+
+/ {
+	model = "Sipeed Lichee RV Dock";
+	compatible = "sipeed,lichee-rv-dock", "sipeed,lichee-rv",
+		     "allwinner,sun20i-d1";
+
+	aliases {
+		mmc1 = &mmc1;
+	};
+
+	dmic-card {
+		compatible = "simple-audio-card";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		simple-audio-card,dai-link@0 {
+			format = "pdm";
+			frame-master = <&link0_cpu>;
+			bitclock-master = <&link0_cpu>;
+
+			link0_cpu: cpu {
+				sound-dai = <&dmic>;
+			};
+
+			link0_codec: codec {
+				sound-dai = <&dmic_codec>;
+			};
+		};
+	};
+
+	dmic_codec: dmic-codec {
+		compatible = "dmic-codec";
+		num-channels = <2>;
+		#sound-dai-cells = <0>;
+	};
+
+	hdmi_connector: connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	wifi_pwrseq: wifi-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&gpio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
+	};
+};
+
+&codec {
+	allwinner,routing = "Internal Speaker", "HPOUTL",
+			    "Internal Speaker", "HPOUTR",
+			    "LINEINL", "HPOUTL",
+			    "LINEINR", "HPOUTR",
+			    "MICIN3", "Internal Microphone",
+			    "Internal Microphone", "HBIAS";
+	allwinner,widgets = "Microphone", "Internal Microphone",
+			    "Speaker", "Internal Speaker";
+	status = "okay";
+};
+
+&de {
+	status = "okay";
+};
+
+&dmic {
+	pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&gpio {
+	dmic_pb11_d0_pin: dmic-pb11-d0-pin {
+		pins = "PB11";
+		function = "dmic";
+	};
+
+	dmic_pe17_clk_pin: dmic-pe17-clk-pin {
+		pins = "PE17";
+		function = "dmic";
+	};
+
+	ledc_pc0_pin: ledc-pc0-pin {
+		pins = "PC0";
+		function = "ledc";
+	};
+};
+
+&hdmi {
+	status = "okay";
+
+	port {
+		hdmi_out_con: endpoint {
+			remote-endpoint = <&hdmi_con_in>;
+		};
+	};
+};
+
+&hdmi_phy {
+	status = "okay";
+};
+
+&ledc {
+	pinctrl-0 = <&ledc_pc0_pin>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	led@0 {
+		reg = <0x0>;
+		color = <LED_COLOR_ID_RGB>;
+		function = LED_FUNCTION_STATUS;
+	};
+};
+
+&lradc {
+	wakeup-source;
+	status = "okay";
+
+	button-220 {
+		label = "OK";
+		linux,code = <KEY_OK>;
+		channel = <0>;
+		voltage = <220000>;
+	};
+};
+
+&mmc1 {
+	bus-width = <4>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	non-removable;
+	vmmc-supply = <&reg_vcc_3v3>;
+	vqmmc-supply = <&reg_vcc_3v3>;
+	pinctrl-0 = <&mmc1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usbphy {
+	usb1_vbus-supply = <&reg_vcc>;
+};

arch/riscv/dts/sun20i-d1-lichee-rv.dts

@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+#include "sun20i-d1.dtsi"
+#include "sun20i-d1-common-regulators.dtsi"
+
+/ {
+	model = "Sipeed Lichee RV";
+	compatible = "sipeed,lichee-rv", "allwinner,sun20i-d1";
+
+	aliases {
+		mmc0 = &mmc0;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			function = LED_FUNCTION_STATUS;
+			gpios = <&gpio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
+		};
+	};
+
+	reg_vdd_cpu: vdd-cpu {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd-cpu";
+		regulator-min-microvolt = <900000>;
+		regulator-max-microvolt = <900000>;
+		vin-supply = <&reg_vcc>;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&reg_vdd_cpu>;
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&mmc0 {
+	broken-cd;
+	bus-width = <4>;
+	disable-wp;
+	vmmc-supply = <&reg_vcc_3v3>;
+	vqmmc-supply = <&reg_vcc_3v3>;
+	pinctrl-0 = <&mmc0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-0 = <&spi0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0_pb8_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usbphy {
+	usb0_vbus-supply = <&reg_vcc>;
+	usb0_vbus_det-gpios = <&gpio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
+	status = "okay";
+};

arch/riscv/dts/sun20i-d1-nezha.dts

@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pwm/pwm.h>
+
+#include "sun20i-d1.dtsi"
+#include "sun20i-d1-common-regulators.dtsi"
+
+/ {
+	model = "Allwinner D1 Nezha";
+	compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
+
+	aliases {
+		ethernet0 = &emac;
+		mmc0 = &mmc0;
+		mmc1 = &mmc1;
+		mmc2 = &mmc2;
+		serial0 = &uart0;
+		spi0 = &spi0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	hdmi_connector: connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
+	reg_usbvbus: usbvbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usbvbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
+		enable-active-high;
+		vin-supply = <&reg_vcc>;
+	};
+
+	reg_vdd_cpu: vdd-cpu {
+		compatible = "pwm-regulator";
+		pwms = <&pwm 0 50000 0>;
+		pwm-supply = <&reg_vcc>;
+		regulator-name = "vdd-cpu";
+		regulator-min-microvolt = <810000>;
+		regulator-max-microvolt = <1160000>;
+	};
+
+	wifi_pwrseq: wifi-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&gpio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
+	};
+};
+
+&codec {
+	allwinner,routing = "Headphone Jack", "HPOUTL",
+			    "Headphone Jack", "HPOUTR",
+			    "LINEINL", "HPOUTL",
+			    "LINEINR", "HPOUTR",
+			    "MICIN3", "Headset Microphone",
+			    "Headset Microphone", "HBIAS";
+	allwinner,widgets = "Microphone", "Headset Microphone",
+			    "Headphone", "Headphone Jack";
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&reg_vdd_cpu>;
+};
+
+&de {
+	status = "okay";
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&ehci1 {
+	status = "okay";
+};
+
+&emac {
+	pinctrl-0 = <&rgmii_pe_pins>;
+	pinctrl-names = "default";
+	phy-handle = <&ext_rgmii_phy>;
+	phy-mode = "rgmii-id";
+	phy-supply = <&reg_vcc_3v3>;
+	status = "okay";
+};
+
+&gpio {
+	i2s2_pb_pins: i2s2-pb-pins {
+		pins = "PB5", "PB6", "PB7";
+		function = "i2s2";
+	};
+
+	i2s2_pb3_din_pin: i2s2-pb3-din-pin {
+		pins = "PB3";
+		function = "i2s2_din";
+	};
+
+	i2s2_pb4_dout_pin: i2s2-pb4-dout-pin {
+		pins = "PB4";
+		function = "i2s2_dout";
+	};
+
+	ledc_pc0_pin: ledc-pc0-pin {
+		pins = "PC0";
+		function = "ledc";
+	};
+
+	pwm0_pd16_pin: pwm0-pd16-pin {
+		pins = "PD16";
+		function = "pwm";
+	};
+
+	pwm2_pd18_pin: pwm2-pd18-pin {
+		pins = "PD18";
+		function = "pwm";
+	};
+
+	pwm7_pd22_pin: pwm7-pd22-pin {
+		pins = "PD22";
+		function = "pwm";
+	};
+
+	spdif_pd22_pin: spdif-pd22-pin {
+		pins = "PD22";
+		function = "spdif";
+	};
+};
+
+&hdmi {
+	status = "okay";
+
+	port {
+		hdmi_out_con: endpoint {
+			remote-endpoint = <&hdmi_con_in>;
+		};
+	};
+};
+
+&hdmi_phy {
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-0 = <&i2c0_pb10_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_pb0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	pcf8574a: gpio@38 {
+		compatible = "nxp,pcf8574a";
+		#address-cells = <0>;
+		reg = <0x38>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupts-extended = <&gpio 1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&i2s2 {
+	pinctrl-0 = <&i2s2_pb_pins>, <&i2s2_pb3_din_pin>, <&i2s2_pb4_dout_pin>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&ledc {
+	pinctrl-0 = <&ledc_pc0_pin>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	led@0 {
+		reg = <0x0>;
+		color = <LED_COLOR_ID_RGB>;
+		function = LED_FUNCTION_INDICATOR;
+	};
+};
+
+&lradc {
+	wakeup-source;
+	status = "okay";
+
+	button-160 {
+		label = "OK";
+		linux,code = <KEY_OK>;
+		channel = <0>;
+		voltage = <160000>;
+	};
+};
+
+&mdio {
+	ext_rgmii_phy: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
+};
+
+&mmc0 {
+	bus-width = <4>;
+	cd-gpios = <&gpio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+	disable-wp;
+	vmmc-supply = <&reg_vcc_3v3>;
+	vqmmc-supply = <&reg_vcc_3v3>;
+	pinctrl-0 = <&mmc0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&mmc1 {
+	bus-width = <4>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	non-removable;
+	vmmc-supply = <&reg_vcc_3v3>;
+	vqmmc-supply = <&reg_vcc_3v3>;
+	pinctrl-0 = <&mmc1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	xr829: wifi@1 {
+		reg = <1>;
+		host-wake-gpios = <&gpio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */
+	};
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&ohci1 {
+	status = "okay";
+};
+
+&pwm {
+	pinctrl-0 = <&pwm0_pd16_pin>, <&pwm2_pd18_pin>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&spdif {
+	pinctrl-0 = <&spdif_pd22_pin>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-0 = <&spi0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	flash@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "boot0";
+				reg = <0x00000000 0x00100000>;
+			};
+
+			partition@100000 {
+				label = "uboot";
+				reg = <0x00100000 0x00300000>;
+			};
+
+			partition@400000 {
+				label = "secure_storage";
+				reg = <0x00400000 0x00100000>;
+			};
+
+			partition@500000 {
+				label = "sys";
+				reg = <0x00500000 0x0fb00000>;
+			};
+		};
+	};
+};
+
+&spi1 {
+	pinctrl-0 = <&spi1_pd_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0_pb8_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	bluetooth {
+		compatible = "xradio,xr829-bt";
+		device-wakeup-gpios = <&gpio 6 16 GPIO_ACTIVE_LOW>; /* PG16 */
+		interrupts-extended = <&gpio 6 17 IRQ_TYPE_LEVEL_LOW>; /* PG17 */
+		interrupt-names = "wakeup";
+		reset-gpios = <&gpio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
+	};
+};
+
+&usb_otg {
+	dr_mode = "otg";
+	status = "okay";
+};
+
+&usbphy {
+	usb0_id_det-gpios = <&gpio 3 21 GPIO_ACTIVE_LOW>; /* PD21 */
+	usb0_vbus_det-gpios = <&gpio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
+	usb0_vbus-supply = <&reg_usbvbus>;
+	usb1_vbus-supply = <&reg_vcc>;
+	status = "okay";
+};

arch/riscv/dts/sunxi-u-boot.dtsi

@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "binman.dtsi"
+
+&mbus {
+	status = "disabled";
+};

arch/riscv/include/asm/bitops.h

@@ -78,6 +78,7 @@ static inline int __test_and_set_bit(int nr, void *addr)
 	return retval;
 }
 
+#define test_and_clear_bit __test_and_clear_bit
 static inline int __test_and_clear_bit(int nr, void *addr)
 {
 	int mask, retval;

arch/riscv/include/asm/io.h

@@ -114,6 +114,7 @@ static inline u16 readw(const volatile void __iomem *addr)
 	return val;
 }
 
+#define readl_relaxed readl
 static inline u32 readl(const volatile void __iomem *addr)
 {
 	u32	val;
@@ -246,6 +247,7 @@ static inline u64 readq(const volatile void __iomem *addr)
 #define insb(p, d, l)			readsb(__io(p), d, l)
 #define insw(p, d, l)			readsw(__io(p), d, l)
 #define insl(p, d, l)			readsl(__io(p), d, l)
+#endif
 
 static inline void readsb(unsigned int *addr, void *data, int bytelen)
 {
@@ -336,7 +338,6 @@ static inline void writesl(unsigned int *addr, const void *data, int longlen)
 		longlen--;
 	}
 }
-#endif
 
 #define outb_p(val, port)		outb((val), (port))
 #define outw_p(val, port)		outw((val), (port))

arch/riscv/include/asm/processor.h

@@ -23,4 +23,6 @@
  *     no one uses the macros defined in this head file.
  **************************************************************/
 
+#define cpu_relax()			barrier()
+
 #endif /* __ASM_RISCV_PROCESSOR_H */

arch/riscv/lib/cache.c

@@ -20,7 +20,7 @@ __weak void flush_dcache_range(unsigned long start, unsigned long end)
 {
 }
 
-void invalidate_icache_range(unsigned long start, unsigned long end)
+__weak void invalidate_icache_range(unsigned long start, unsigned long end)
 {
 	/*
 	 * RISC-V does not have an instruction for invalidating parts of the

board/sunxi/Kconfig

@@ -1,5 +1,24 @@
+menu "Board-specific options"
+	depends on ARCH_SUNXI || TARGET_SUNXI
+
+choice
+	prompt "sunxi SoC Variant"
+
+config MACH_SUN20I
+	bool "sun20i (Allwinner D1)"
+	depends on RISCV
+	select GENERIC_RISCV
+	select SPL_DM if SPL
+	imply SYSRESET_SBI
+
+endchoice
+
+config NR_DRAM_BANKS
+	default 1
+
 choice
 	prompt "SPL Image Type"
+	depends on SPL
 	default SPL_IMAGE_TYPE_SUNXI_EGON
 
 config SPL_IMAGE_TYPE_SUNXI_EGON
@@ -22,3 +41,69 @@ config SPL_IMAGE_TYPE
 	string
 	default "sunxi_egon" if SPL_IMAGE_TYPE_SUNXI_EGON
 	default "sunxi_toc0" if SPL_IMAGE_TYPE_SUNXI_TOC0
+
+config SPL_MAX_SIZE
+	hex
+	default SUNXI_SRAM_SIZE
+
+config SPL_OPENSBI_LOAD_ADDR
+	default 0x40000000
+
+config SUNXI_SRAM_ADDRESS
+	hex
+	default 0x20000 if MACH_SUN20I
+
+config SUNXI_SRAM_SIZE
+	hex
+	default 0x28000 if MACH_SUN20I
+
+config SYS_BOARD
+	default "sunxi"
+
+config SYS_CONFIG_NAME
+	default "sunxi-common" if MACH_SUN20I
+
+config SYS_CPU
+	default "generic" if MACH_SUN20I
+
+config SYS_SOC
+	default "sunxi"
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select CLK
+	select DM_ETH if NET
+	select DM_GPIO
+	select DM_I2C if I2C
+	select DM_SERIAL
+	select DM_SPI if SPI
+	select GPIO
+	select MMC_SUNXI_HAS_NEW_MODE if MMC_SUNXI
+	select OF_HAS_PRIOR_STAGE
+	select PHY_SUN4I_USB if USB
+	select PINCTRL
+	select SPL_CLK if SPL_DM
+	select SPL_GPIO if SPL_DM
+	select SPL_OF_CONTROL if SPL_DM
+	select SPL_PINCTRL if SPL_DM
+	select SPL_SEPARATE_BSS if SPL
+	select SUPPORT_SPL
+	imply CMD_MMC
+	imply CMD_USB
+	imply DISTRO_DEFAULTS
+	imply FIT
+	imply MMC
+	imply SPL
+	imply SPL_SPI if SPI
+	imply SPL_MMC if MMC
+	imply SUNXI_GPIO
+	imply SYS_I2C_MVTWSI
+	imply SYS_NS16550
+	imply SYSRESET
+	imply USB_EHCI_GENERIC
+	imply USB_EHCI_HCD
+	imply USB_OHCI_GENERIC
+	imply USB_OHCI_HCD
+	imply WDT
+
+endmenu

board/sunxi/Makefile

@@ -6,7 +6,8 @@
 #
 # (C) Copyright 2000-2003
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-y	+= board.o
+obj-$(CONFIG_ARCH_SUNXI)	+= board.o
+obj-$(CONFIG_TARGET_SUNXI)	+= board-riscv.o
 obj-$(CONFIG_SUN7I_GMAC)	+= gmac.o
 obj-$(CONFIG_MACH_SUN4I)	+= dram_sun4i_auto.o
 obj-$(CONFIG_MACH_SUN5I)	+= dram_sun5i_auto.o

board/sunxi/board-riscv.c

@@ -0,0 +1,23 @@
+#include <common.h>
+#include <cpu.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void *board_fdt_blob_setup(int *err)
+{
+	*err = 0;
+
+	return (void *)(ulong)gd->arch.firmware_fdt_addr;
+}
+
+int board_init(void)
+{
+	/* https://lore.kernel.org/u-boot/31587574-4cd1-02da-9761-0134ac82b94b@sholland.org/ */
+	return cpu_probe_all();
+}
+
+uint32_t spl_boot_device(void)
+{
+	return BOOT_DEVICE_MMC1;
+}

board/sunxi/board.c

@@ -19,6 +19,7 @@
 #include <init.h>
 #include <log.h>
 #include <mmc.h>
+#include <remoteproc.h>
 #include <axp_pmic.h>
 #include <generic-phy.h>
 #include <phy-sun4i-usb.h>
@@ -215,10 +216,6 @@ int board_init(void)
 	}
 #endif /* !CONFIG_ARM64 && !CONFIG_MACH_SUNIV */
 
-	ret = axp_gpio_init();
-	if (ret)
-		return ret;
-
 	/* strcmp() would look better, but doesn't get optimised away. */
 	if (CONFIG_SATAPWR[0]) {
 		satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
@@ -306,7 +303,7 @@ int dram_init(void)
 	return 0;
 }
 
-#if defined(CONFIG_NAND_SUNXI)
+#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
 static void nand_pinmux_setup(void)
 {
 	unsigned int pin;
@@ -342,9 +339,6 @@ void board_nand_init(void)
 {
 	nand_pinmux_setup();
 	nand_clock_setup();
-#ifndef CONFIG_SPL_BUILD
-	sunxi_nand_init();
-#endif
 }
 #endif
 
@@ -860,6 +854,13 @@ int board_late_init(void)
 	usb_ether_init();
 #endif
 
+#ifdef SUNXI_SCP_BASE
+	if (!rproc_load(0, SUNXI_SCP_BASE, SUNXI_SCP_MAX_SIZE)) {
+		puts("Starting SCP...\n");
+		rproc_start(0);
+	}
+#endif
+
 	return 0;
 }
 

boot/Kconfig

@@ -477,7 +477,10 @@ config SYS_TEXT_BASE
 	default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3
 	default 0x81700000 if MACH_SUNIV
 	default 0x2a000000 if MACH_SUN9I
-	default 0x42e00000 if MACH_SUN8I_V3S
+	# We should use the smaller address like V3S to support D1s,
+	# but this is a breaking change.
+	default 0x4a000000 if MACH_SUN20I
+	default 0x42e00000 if MACH_SUN8I_V3S || MACH_SUN20I
 	default 0x4a000000 if ARCH_SUNXI
 	hex "Text Base"
 	help

boot/image.c

@@ -179,6 +179,7 @@ static const table_entry_t uimage_type[] = {
 	{	IH_TYPE_COPRO, "copro", "Coprocessor Image"},
 	{	IH_TYPE_SUNXI_EGON, "sunxi_egon",  "Allwinner eGON Boot Image" },
 	{	IH_TYPE_SUNXI_TOC0, "sunxi_toc0",  "Allwinner TOC0 Boot Image" },
+	{	IH_TYPE_SUNXI_TOC1, "sunxi_toc1",  "Allwinner TOC1 Boot Image" },
 	{	-1,		    "",		  "",			},
 };
 

common/spl/Kconfig

@@ -175,7 +175,7 @@ config SPL_TEXT_BASE
 	hex "SPL Text Base"
 	default ISW_ENTRY_ADDR if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
 	default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
-	default 0x20060 if SUN50I_GEN_H6
+	default 0x20060 if SUN50I_GEN_H6 || MACH_SUN20I
 	default 0x00060 if ARCH_SUNXI
 	default 0xfffc0000 if ARCH_ZYNQMP
 	default 0x0
@@ -477,8 +477,7 @@ config SPL_MD5
 config SPL_FIT_IMAGE_TINY
 	bool "Remove functionality from SPL FIT loading to reduce size"
 	depends on SPL_FIT
-	default y if MACH_SUN50I || MACH_SUN50I_H5 || SUN50I_GEN_H6
+	default y if ARCH_IMX8M || ARCH_SUNXI
-	default y if ARCH_IMX8M
 	help
 	  Enable this to reduce the size of the FIT image loading code
 	  in SPL, if space for the SPL binary is very tight.
@@ -1324,7 +1323,7 @@ config SPL_OPTEE_IMAGE
 
 config SPL_OPENSBI
 	bool "Support RISC-V OpenSBI"
-	depends on RISCV && SPL_RISCV_MMODE && RISCV_SMODE
+	depends on RISCV && SPL_RISCV_MMODE && RISCV_SMODE && SPL_LOAD_FIT
 	help
 	  OpenSBI is an open-source implementation of the RISC-V Supervisor Binary
 	  Interface (SBI) specification. U-Boot supports the OpenSBI FW_DYNAMIC

configs/A10-OLinuXino-Lime_defconfig

@@ -23,3 +23,4 @@ CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
+CONFIG_DM_REGULATOR_FIXED=y

configs/A10s-OLinuXino-M_defconfig

@@ -7,7 +7,7 @@ CONFIG_DRAM_CLK=432
 CONFIG_MMC0_CD_PIN="PG1"
 CONFIG_MMC1_CD_PIN="PG13"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=1
-CONFIG_USB1_VBUS_PIN="PB10"
+CONFIG_DM_REGULATOR_FIXED=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
 CONFIG_SYS_I2C_MVTWSI=y

configs/A13-OLinuXinoM_defconfig

@@ -6,7 +6,7 @@ CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_EMR1=0
 CONFIG_MMC0_CD_PIN="PG0"
-CONFIG_USB1_VBUS_PIN="PG11"
+CONFIG_DM_REGULATOR_FIXED=y
 # CONFIG_VIDEO_HDMI is not set
 CONFIG_VIDEO_VGA_VIA_LCD=y
 CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y

configs/A13-OLinuXino_defconfig

@@ -6,8 +6,7 @@ CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_EMR1=0
 CONFIG_MMC0_CD_PIN="PG0"
-CONFIG_USB0_VBUS_DET="PG1"
+CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_USB1_VBUS_PIN="PG11"
 CONFIG_AXP_GPIO=y
 # CONFIG_VIDEO_HDMI is not set
 CONFIG_VIDEO_VGA_VIA_LCD=y

configs/A20-OLinuXino-Lime2-eMMC_defconfig

@@ -6,8 +6,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="PC17"
+CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
 CONFIG_SATAPWR="PC3"
 CONFIG_SPL_SPI_SUNXI=y

configs/A20-OLinuXino-Lime2_defconfig

@@ -5,8 +5,7 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
-CONFIG_USB0_VBUS_PIN="PC17"
+CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
 CONFIG_SATAPWR="PC3"
 CONFIG_AHCI=y

configs/A20-OLinuXino-Lime_defconfig

@@ -23,3 +23,4 @@ CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
+CONFIG_DM_REGULATOR_FIXED=y

configs/A20-OLinuXino_MICRO-eMMC_defconfig

@@ -26,3 +26,4 @@ CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
+CONFIG_DM_REGULATOR_FIXED=y

configs/A20-OLinuXino_MICRO_defconfig

@@ -27,3 +27,4 @@ CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
+CONFIG_DM_REGULATOR_FIXED=y

configs/A20-Olimex-SOM-EVB_defconfig

@@ -7,8 +7,7 @@ CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC3_CD_PIN="PH0"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=3
-CONFIG_USB0_VBUS_PIN="PB9"
+CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_SATAPWR="PC3"
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

configs/A20-Olimex-SOM204-EVB-eMMC_defconfig

@@ -6,8 +6,7 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="PC17"
+CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
 CONFIG_SATAPWR="PC3"
 CONFIG_GMAC_TX_DELAY=4

configs/A20-Olimex-SOM204-EVB_defconfig

@@ -5,8 +5,7 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=384
 CONFIG_MMC0_CD_PIN="PH1"
-CONFIG_USB0_VBUS_PIN="PC17"
+CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_USB0_VBUS_DET="PH5"
 CONFIG_I2C1_ENABLE=y
 CONFIG_SATAPWR="PC3"
 CONFIG_GMAC_TX_DELAY=4

configs/A33-OLinuXino_defconfig

@@ -7,9 +7,8 @@ CONFIG_DRAM_CLK=432
 CONFIG_DRAM_ZQ=15291
 CONFIG_DRAM_ODT_EN=y
 CONFIG_MMC0_CD_PIN="PB4"
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_REGULATOR_AXP=y
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_REGULATOR_AXP_USB_POWER=y
-CONFIG_USB0_ID_DET="PB3"
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_DCLK_PHASE=0

configs/Ainol_AW1_defconfig

@@ -6,8 +6,8 @@ CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_ZQ=123
 CONFIG_MMC0_CD_PIN="PH1"
-CONFIG_USB0_VBUS_PIN="PB9"
+CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_REGULATOR_AXP_USB_POWER=y
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:40000,le:87,ri:112,up:38,lo:141,hs:1,vs:1,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_POWER="PH8"

configs/Ampe_A76_defconfig

@@ -5,9 +5,7 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=432
 CONFIG_MMC0_CD_PIN="PG0"
-CONFIG_USB0_VBUS_PIN="PG12"
+CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB0_ID_DET="PG2"
 CONFIG_AXP_GPIO=y
 # CONFIG_VIDEO_HDMI is not set
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"

configs/Auxtek-T003_defconfig

@@ -5,7 +5,7 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_EMR1=0
-CONFIG_USB1_VBUS_PIN="PB10"
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_VIDEO_COMPOSITE=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y

configs/Auxtek-T004_defconfig

@@ -4,7 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004"
 CONFIG_SPL=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=432
-CONFIG_USB1_VBUS_PIN="PG13"
+CONFIG_DM_REGULATOR_FIXED=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y
 CONFIG_SYS_I2C_MVTWSI=y

configs/Bananapi_M2_Ultra_defconfig

@@ -7,9 +7,8 @@ CONFIG_DRAM_CLK=576
 CONFIG_MACPWR="PA17"
 CONFIG_MMC0_CD_PIN="PH13"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB1_VBUS_PIN="PH23"
-CONFIG_USB2_VBUS_PIN="PH23"
 # CONFIG_HAS_ARMV7_SECURE_BASE is not set
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_AHCI=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_I2C=y

configs/Bananapi_defconfig

@@ -23,3 +23,4 @@ CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
+CONFIG_DM_REGULATOR_FIXED=y

configs/Bananapi_m2m_defconfig

@@ -8,7 +8,6 @@ CONFIG_DRAM_ZQ=15291
 CONFIG_DRAM_ODT_EN=y
 CONFIG_MMC0_CD_PIN="PB4"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_ID_DET="PH8"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_USB_EHCI_HCD=y

configs/Bananapro_defconfig

@@ -5,8 +5,7 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=432
 CONFIG_MACPWR="PH23"
-CONFIG_USB1_VBUS_PIN="PH0"
+CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_USB2_VBUS_PIN="PH1"
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_GMAC_TX_DELAY=3
 CONFIG_AHCI=y

configs/CHIP_defconfig

@@ -4,7 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
 CONFIG_SPL=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
-CONFIG_USB0_VBUS_PIN="PB10"
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_CHIP_DIP_SCAN=y
 CONFIG_SPL_I2C=y

configs/CHIP_pro_defconfig

@@ -4,7 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-gr8-chip-pro"
 CONFIG_SPL=y
 CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
-CONFIG_USB0_VBUS_PIN="PB10"
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SPL_I2C=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MTDPARTS=y

configs/CSQ_CS908_defconfig

@@ -4,8 +4,6 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908"
 CONFIG_SPL=y
 CONFIG_MACH_SUN6I=y
 CONFIG_DRAM_CLK=432
-CONFIG_USB1_VBUS_PIN=""
-CONFIG_USB2_VBUS_PIN=""
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_PHY_REALTEK=y
 CONFIG_ETH_DESIGNWARE=y
@@ -16,3 +14,4 @@ CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
+CONFIG_DM_REGULATOR_FIXED=y

configs/Chuwi_V7_CW0825_defconfig

@@ -5,9 +5,7 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_EMR1=4
-CONFIG_USB0_VBUS_PIN="PB9"
+CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_USB0_VBUS_DET="PH5"
-CONFIG_USB0_ID_DET="PH4"
 CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:51000,le:19,ri:300,up:6,lo:31,hs:1,vs:1,sync:3,vmode:0"
 CONFIG_VIDEO_LCD_POWER="PH8"
 CONFIG_VIDEO_LCD_BL_EN="PH7"

configs/Colombus_defconfig

@@ -5,7 +5,6 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN6I=y
 CONFIG_DRAM_CLK=240
 CONFIG_DRAM_ZQ=251
-CONFIG_USB1_VBUS_PIN=""
 CONFIG_I2C0_ENABLE=y
 CONFIG_AXP_GPIO=y
 CONFIG_VIDEO_LCD_MODE="x:2048,y:1536,depth:24,pclk_khz:208000,le:5,ri:150,up:9,lo:24,hs:5,vs:1,sync:3,vmode:0"
@@ -27,3 +26,4 @@ CONFIG_SUN7I_GMAC=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
+CONFIG_DM_REGULATOR_FIXED=y

configs/Cubieboard2_defconfig

@@ -20,3 +20,4 @@ CONFIG_SUN7I_GMAC=y
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
+CONFIG_DM_REGULATOR_FIXED=y

configs/Cubieboard4_defconfig

@@ -6,11 +6,9 @@ CONFIG_MACH_SUN9I=y
 CONFIG_DRAM_CLK=672
 CONFIG_MMC0_CD_PIN="PH18"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_REGULATOR_AXP=y
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_REGULATOR_AXP_USB_POWER=y
-CONFIG_USB0_ID_DET="PH16"
+CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_USB1_VBUS_PIN="PH14"
-CONFIG_USB3_VBUS_PIN="PH15"
 CONFIG_AXP_GPIO=y
 CONFIG_SYS_I2C_SUN8I_RSB=y
 CONFIG_AXP809_POWER=y

configs/Cubieboard_defconfig

@@ -18,3 +18,4 @@ CONFIG_SUN4I_EMAC=y
 CONFIG_SCSI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
+CONFIG_DM_REGULATOR_FIXED=y

configs/Cubietruck_defconfig

@@ -5,9 +5,7 @@ CONFIG_SPL=y
 CONFIG_MACH_SUN7I=y
 CONFIG_DRAM_CLK=432
 CONFIG_MMC0_CD_PIN="PH1"
-CONFIG_USB0_VBUS_PIN="PH17"
+CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_USB0_VBUS_DET="PH22"
-CONFIG_USB0_ID_DET="PH19"
 CONFIG_VIDEO_VGA=y
 CONFIG_SATAPWR="PH12"
 CONFIG_GMAC_TX_DELAY=1

configs/Cubietruck_plus_defconfig

@@ -7,11 +7,9 @@ CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=15355
 CONFIG_DRAM_ODT_EN=y
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
-CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_REGULATOR_AXP=y
-CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_REGULATOR_AXP_USB_POWER=y
-CONFIG_USB0_ID_DET="PH11"
+CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_USB1_VBUS_PIN="PD29"
-CONFIG_USB2_VBUS_PIN="PL6"
 CONFIG_I2C0_ENABLE=y
 CONFIG_AXP_GPIO=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

configs/Empire_electronix_d709_defconfig

@@ -6,9 +6,7 @@ CONFIG_MACH_SUN5I=y
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_EMR1=0
 CONFIG_MMC0_CD_PIN="PG0"
-CONFIG_USB0_VBUS_PIN="PG12"
+CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_USB0_VBUS_DET="PG1"
-CONFIG_USB0_ID_DET="PG2"
 CONFIG_AXP_GPIO=y
 # CONFIG_VIDEO_HDMI is not set
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"