26008 Commits

Author SHA1 Message Date
Weizhao Ouyang
12ccdcd79b firmware: psci: Fix bind_smccc_features psci check
According to PSCI specification DEN0022F, PSCI_FEATURES is used to check
whether the SMCCC is implemented by discovering SMCCC_VERSION.

Signed-off-by: Weizhao Ouyang <o451686892@gmail.com>
2024-03-13 12:40:43 -04:00
Vignesh Raghavendra
558fbddbb4 dma: ti: k3-udma: Add DMA PSIL mappings for AM62P and J722S
Add PSIL data for the AM62P and the J722S SoC family. The PSIL mapping
for the J722S is the same except for the extra instances of the CSI-RX.
So let's reuse the same file for both the AM62P and J722S.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
[bb@ti.com: rebased to U-Boot v2024.01]
Signed-off-by: Bryan Brattlof <bb@ti.com>
2024-03-13 10:10:05 -04:00
Hari Nagalla
e17dc351a6 firmware: ti_sci_static_data: add static DMA channel data
Include the static DMA channel data for ti_sci

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
2024-03-13 10:10:05 -04:00
Bryan Brattlof
55e7e2e0e5 ram: k3-ddrss: enable the am62ax's DDR controller for am62px
The am62px family of SoCs uses the same DDR controller as found on the
am62ax family. Enable this option when building for the am62px family

Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
2024-03-13 10:10:04 -04:00
Bryan Brattlof
1bcc7a4d7d arm: mach-k3: am62px: introduce clock and device files for wkup spl
Include the clock and lpsc tree files needed for the wkup spl to
initialize the proper PLLs and power domains to boot the SoC.

Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
2024-03-13 10:10:04 -04:00
Bryan Brattlof
c59d3746d6 power: domain: ti: use IS_ENABLED macro
Cleanup this list and standardize on using the IS_ENABLED macro for the
power domain data list.

Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Signed-off-by: Bryan Brattlof <bb@ti.com>
2024-03-13 10:10:04 -04:00
Bryan Brattlof
026c972fa3 soc: add info to identify the am62p SoC family
Include the part number for TI's am62px family of SoCs so we can
properly identify it during boot

Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
2024-03-13 10:10:04 -04:00
Quentin Schulz
9f5df9a3ef rockchip: include asm/io.h directly in asm/arch-rockchip/hardware.h
The different macros use writel which is defined in asm/io.h, so let's
include the header so users of hardware.h do not need to include
asm/io.h as well.

While at it, remove asm/io.h includes wherever
asm/arch-rockchip/hardware.h is included already.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2024-03-13 18:15:52 +08:00
Quentin Schulz
eda2c8736e rockchip: migrate hardware.h inclusion into appropriate files
hardware.h is only defining macros which are "wrappers" around writel().

writel() is however not available in hardware.h, <asm/io.h> needs to be
included. This means in order to use the wrappers in hardware.h, one
also needs to include the <asm/io.h> header.

However, this cannot be done currently because hardware.h is included in
include/configs files, which are implicitly included by every code file
by default, which makes the compilation of arch/arm/cpu/armv8/u-boot.lds
fail because ALIGN (the ARM assembly directive) got redefined by some
of the include files coming from <asm.io.h>.

Because nothing in the include/configs file actually use hardware.h,
let's remove the inclusion of hardware.h from the include/configs files
and explicitly add it wherever it is required.

This prepares for the next commit where <asm/io.h> will be included in
hardware.h.

Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2024-03-13 18:14:19 +08:00
Venkatesh Yadav Abbarapu
0508653ea6 mtd: nand: arasan: Fix the crash caused by use after free
The below exception observed on QEMU, as it doesn't support
NAND controller.

"Synchronous Abort" handler, esr 0x96000005, far 0x17acfc878
elr: 000000000803ad40 lr : 000000000805f438 (reloc)
elr: 000000007fcb4d40 lr : 000000007fcd9438
x0 : 000000007bbfc880 x1 : 00000000ff100000
x2 : 000000007fcf059c x3 : 000000007bbfc870
x4 : 000000007fd9a388 x5 : 000000017acfc870
x6 : 0000000000000000 x7 : 000000007bbfd0e0
x8 : 0000000000003dd4 x9 : 000000007bbeec0c
x10: 0000000000000001 x11: 0000000000003f8c
x12: 000000007bbeecfc x13: 000000007bbeeeb0
x14: 000000007bbeeeb0 x15: 000000007bbee474
x16: 000000007fcef18c x17: 0000000000000000
x18: 000000007bbf9d70 x19: 000000007bbfc888
x20: 000000007bbfc870 x21: 000000007fd68ddb
x22: 00000000ffffffed x23: 000000007bbfc878
x24: 0000000000000000 x25: 0000000000000000
x26: 0000000000000000 x27: 0000000000000000
x28: 0000000000000000 x29: 000000007bbeed10

Code: 927ff8c1 924000c6 8b010065 f9400887 (f94004a2)
Resetting CPU ...

The crash is caused by the use after free.
Updating the correct return codes rather than hardcoding.
Fixes: 3dd0f8cccd6d ("mtd: nand: Remove hardcoded base address of nand")

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20240306033404.18537-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-03-12 16:07:24 +01:00
Venkatesh Yadav Abbarapu
602b879efd mtd: nand: arasan: Print warning for unsupported ecc modes
Currently only hw ecc is supported in U-Boot. If any other ecc mode is
given in DT, it simply through an error. So better print
what is being done.

Revert this patch once soft ecc support is fixed in future.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20240306032703.17508-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2024-03-12 16:06:45 +01:00
Heinrich Schuchardt
25e7d4bf64 serial: move sbi_dbcn_available to .data section
U-Boot SPL loads the device-tree directly behind main U-Boot overlapping
the .bss section. reserve_fdt() is called in board_init_f() to relocate the
device-tree to a safe location.

Debug UARTs are enabled before board_init_f(). With sbi_dbcn_available in
the .bss section the device-tree is corrupted when _debug_uart_init() is
called in the SBI serial driver. Move the variable to the .data section.

Link: https://bugs.launchpad.net/ubuntu/+source/u-boot/+bug/2054091
Fixes: dfe08374943c ("risc-v: implement DBCN based debug console")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
2024-03-12 14:36:13 +08:00
Tom Rini
20a0ce574d Prepare v2024.04-rc4
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Merge tag 'v2024.04-rc4' into next

Prepare v2024.04-rc4
2024-03-11 15:27:20 -04:00
Tom Rini
0981f8900f Merge https://source.denx.de/u-boot/custodians/u-boot-usb
- Singular quirk DT property rename.
2024-03-09 11:29:48 -05:00
Marek Vasut
91e70367a5 net: phy: Use PHY MDIO address from DT if available
In case the PHY is fully described in DT, use PHY MDIO address
from DT directly instead of always using auto-detection. This
also fixes the behavior of 'mdio list' in such DT setup, which
now prints the PHY connected to the MAC correctly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-09 10:58:48 -05:00
Yang Xiwen
91febe80c9 serial: pl01x: set baudrate when probing
It is found that when DM is enabled, only generic init function is
called in .probe(). Baudrate is never honored. Add a function call
to .setbrg() when probing so that we can update the baudrate of the
serial device.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
2024-03-07 07:59:16 -05:00
Roger Quadros
be2eb3ad8f net: am65-cpsw: cpsw_mdio: Switch to proper DM_MDIO framework
Add a new Kconfig symbol MDIO_TI_CPSW for the CPSW MDIO
driver and build it with proper DM support if enabled.

If MDIO_TI_CPSW is not enabled then we continue to
behave like before.

Clean up MDIO custom handling in am65-cpsw and use
dm_eth_phy_connect() to get the PHY.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Tested-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
2024-03-07 07:59:16 -05:00
Dmitry Baryshkov
3098115155 virtio: fix get_config / set_config for legacy VirtIO targets
The functions virtio_pci_get_config() and virtio_pci_set_config() don't
take the offset into account when reading the config space. For example
this manifests when U-Boot tries to read the MAC address of the VirtIO
networking device. It reads 6 equa bytes instead of the proper addess.

Fix those functions by taking the offset in the config space into
account.

Fixes: 4135e10732a0 ("virtio: Add virtio over pci transport driver")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-03-05 08:37:53 -05:00
Tom Rini
96ca3d362d Merge patch series "Fix driver for misc/atsha204a"
Michał Barnaś <barnas@google.com> says:

Fix the driver to behave like the chip datasheet requires.
Improve wake up function to send low signal on SDA line for at least
60us as chip requires to wake up. Fix sleep function to move the chip
into sleep mode, not into idle mode. Remove unnecessary for loop,
which would never run for more than one iteration.
2024-03-05 08:08:31 -05:00
Michał Barnaś
2a31d71d83 misc: atsha204a: fix wakeup function
The ATSHA204A chip requires SDA line to go low for at least 60us to
wake up the chip. Previous implementation did not meet this requirement
due to the NAK received on bus and not sending the zeroes.
The function to ignore the NAK and send bytes regardless is not
supported in the u-boot making it impossible to wake up the chip
this way.
Instead, the bus speed, if needed, is set to lowest value and the
message is sent to the address 0x0. This way, the address of zero
makes the SDA line go low for about 80us, meeting the required time
to wake up the chip. The zero length packet is not sent by the i2c,
so the one byte is sent to the transfer function, but only the address
is sent anyway.
After sending the zero address, the bus speed is restored to the
previous value if it was slowed down to wake up the chip.

Signed-off-by: Michał Barnaś <barnas@google.com>
2024-03-05 08:08:26 -05:00
Michał Barnaś
6e0d4a7e02 misc: atsha204a: fix sleep function
Fix the sleep function to issue the sleep command instead of idle one.

Signed-off-by: Michał Barnaś <barnas@google.com>
2024-03-05 08:08:26 -05:00
Michał Barnaś
c4841ae405 misc: atsha204a: remove broken for loop
Some previous commit changed the continue statement to return,
making the for loop used to retry waking up the chip to always
return after one iteration. This commit removes the loop, cleaning
the code a little.

Signed-off-by: Michał Barnaś <barnas@google.com>
2024-03-05 08:08:26 -05:00
Tom Rini
485bfe1adb Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-marvell
- net: mv88e6xxx: fix missing SMI address initialization (Marek)
- mvebu: turris_omnia: Enable networking via ethernet switch (Marek)
- mvebu: helios-4: add config fragment for spi booting et al (Josua)
- rng: Add Turris Mox rTWM RNG driver (Max)
2024-03-05 07:08:55 -05:00
Tom Rini
46e3871aa6 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
One fix makes the reboot more robust on some older board, another one
stabilises the initial clock setup on the A10/A20.
Two patches make sure our DRAM init does not actually change the content
of the DRAM array, which allows to use DRAM for Linux' pstore
functionality.
We get SPI support for U-Boot proper for one more SoC, that patch was
lingering around for a while, and should not affect other SoCs, so I am
merging this now.
As an added bonus, we get the defconfig file for a new board, the DT was
already synced from the kernel tree.

The CI looked happy with changes, and I tested them on five different
boards with different SoCs.
2024-03-05 07:08:10 -05:00
Max Resch
d61b485dbd rng: Add Turris Mox rTWM RNG driver
A RNG driver for Armada 3720 boards running the Turris Mox rWTM firmware
from CZ.NIC in the secure processor.

Signed-off-by: Max Resch <resch.max@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-03-05 08:27:59 +01:00
Marek Mojík
faf96b20ee net: mv88e6xxx: fix missing SMI address initialization
The mv88e6xxx driver does not currently initialize the smi_addr field, but
instead keeps the default zero value. This leads to driver being unusable
on devices where the switch is not on address zero of the mdio bus. Fix
this problem by reading the SMI address from device tree.

Signed-off-by: Marek Mojík <marek.mojik@nic.cz>
Reviewed-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2024-03-05 08:27:59 +01:00
Jonas Karlman
52378ba496 usb: xhci-dwc3: Fix support for dis_enblslpm_quirk
No device tree in U-Boot or linux use the wrong spelling used in code.

Use correct property name as defined in dwc3 bindings.

Fixes: 062790f46131 ("usb: xhci-dwc3: Add USB2 PHY configuration")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Marek Vasut <marex@denx.de>
2024-03-05 01:04:21 +01:00
Udit Kumar
7022640c10 dma: ti: k3-udma: Fix ring_idx to pair k3 nav rings
ring_idx was not correctly assigned in case of tflow_id is zero.
Which leads to wrong pairing of DMA for drivers like OSPI.

Fixes: 4312a1dfca26 ("dma: ti: k3-udma: Use ring_idx to pair k3 nav rings")
Reviewed-by: Jai Luthra <j-luthra@ti.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
2024-03-04 13:41:04 -05:00
Siddharth Vadapalli
333031011c dma: ti: k3-udma: Fix error handling for setup_resources() in udma_probe()
In udma_probe() the return value of setup_resources() is stored in the
u32 "ch_count" member of "struct udma_dev", due to which any negative
return value which indicates an error is masked.

Fix this by storing the return value of setup_resources() in the already
declared integer variable "ret", followed by assigning it to the "ch_count"
member of "struct udma_dev" in case of no error.

While at it, change the "return ret" at the end of udma_probe() to a
"return 0", to explicitly indicate that probe was successful.

Fixes: a8837cf43839 ("dma: ti: k3-udma: Query DMA channels allocated from Resource Manager")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org>
2024-03-04 13:41:04 -05:00
Apurva Nandan
691dfbed07 drivers: dma: Add support for J784S4 SoC
Add support for DMA in J784S4 SoC.

Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
2024-03-04 13:41:03 -05:00
Apurva Nandan
952099944d arm: mach-k3: j784s4: Add clk and power support
Add clk and device data which can be used by respective drivers
to configure clocks and PSC.

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
2024-03-04 13:41:03 -05:00
Apurva Nandan
4e3b94d7ba soc: ti: k3-socinfo: Add entry for J784S4 SoC
Add support for J784S4 SoC Identification.

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
2024-03-04 13:41:03 -05:00
Apurva Nandan
20d0554134 arm: mach-k3: Add basic support for J784S4 SoC definition
Add J784S4 initialization files for initial SPL boot.

config SYS_K3_MCU_SCRATCHPAD_BASE default value is same
for J721E, J721S2, J784S4. So combined them into a single
default.

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
[ add firewall configurations and change the R5 MCU scratchpad ]
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
2024-03-04 13:41:03 -05:00
Jonas Karlman
d07d868be3 dm: core: Fix address translation in devfdt_get_addr_index()
During address translation #address/size-cells props are expected to
apply to child nodes. However, devfdt_get_addr_index() incorrectly use
the parent offset of the udevice parent instead of getting the offset of
the node parent. This will work in most cases when there is only one
udevice tied to a node.

On e.g. an Orange Pi R1 Plus TLS board the dwc3-generic (parent) and
dwc3-generic-host (child) udevice is tied to the same node.

In that case both the offset and parent values end up being the same.
As a result, the #address/size-cells props intended for child nodes
incorrectly gets applied to the node itself resulting in wrong addr
being returned, 0x0 instead of 0xff600000.

The following can be seen on console:

  dwc3-generic-host usb@ff600000: this is not a DesignWare USB3 DRD Core
  dwc3-generic-host usb@ff600000: failed to initialize core

Fix this by using the offset of the parent node and not the offset to
the node the parent udevice is tied to.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
2024-03-04 10:25:47 -05:00
Jonas Karlman
1d01440b3f pinctrl: Check pinconfig nodes pre-reloc status recursively
Pinconfig nodes normally bind recursively with PINCTRL_FULL and
PINCONF_RECURSIVE enabled. However, during U-Boot proper pre-relocation
any node marked with e.g. bootph-all will not bind unless its parent is
also marked for pre-reloc.

  group1 {
      pinconf1 {
          bootph-all;
      };
  };

This cause the following warning message to be shown during U-Boot
proper pre-reloc stage on Rockchip devices, e.g on RK3568:

  ns16550_serial serial@fe660000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19

and on RK3328:

  ns16550_serial serial@ff130000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19

Check pinconfig nodes pre-reloc status recursively to fix this and to
make pinconfig_post_bind work same at both U-Boot proper pre-reloc and
at TPL/SPL stage.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
2024-03-04 10:25:41 -05:00
Sébastien Szymanski
9b9f022e73 video: mxsfb: add back imx6ul/imx6ull support
Because of commit bf947d2a4b15 ("imx6ul: synchronise device tree with
linux"), the compatible property of lcdif in imx6ul.dtsi went from

compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";

to

compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif";

without updating the mxsfb driver to match that change.

Add "fsl,imx6sx-lcdif" as a compatible id to fix that.

Fixes: bf947d2a4b15 ("imx6ul: synchronise device tree with linux")
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2024-03-04 08:18:48 -03:00
Maksim Kiselev
2b9d6a1843 spi: sunxi: Add support for R329/D1/R528/T113 SPI controller
These SoCs have two SPI controllers that are quite similar to the SPI
on previous Allwinner SoCs. The main difference is that new SoCs
don't have a clock divider (SPI_CCR register) inside SPI IP.

Instead SPI sample mode should be configured depending on the input clock.

For now SPI input clock source selection is not supported by this driver,
and only HOSC@24MHz can be used as input clock. Therefore, according to
the, manual we could change the SPI sample mode from delay half
cycle(default) to normal.

This patch adds a quirk for this kind of SPI controllers

Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Tested-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2024-03-03 23:43:43 +00:00
Tom Rini
eac52e4be4 Merge patch series "ARM: renesas: Rename R-Mobile to Renesas"
Marek Vasut <marek.vasut+renesas@mailbox.org> says:

Rename R-Mobile to Renesas all over the place because the chips are
made by Renesas, while only a subset of them is from the R-Mobile line.
2024-03-02 14:30:25 -05:00
Marek Vasut
0afbd11325 mmc: renesas-sdhi: Rename rmobile_is_gen3_mmc0() to rcar_is_gen3_mmc0()
Rename rmobile_is_gen3_mmc0() to rcar_is_gen3_mmc0() because
this particular function is specific to Renesas R-Car Gen3.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:37 -05:00
Marek Vasut
f9aabd4579 ARM: renesas: Rename ARCH_RMOBILE to ARCH_RENESAS
Rename ARCH_RMOBILE to ARCH_RENESAS because all the chips are made
by Renesas, while only a subset of them is from the R-Mobile
line.

Use the following command to perform the rename:

"
$ git grep -l 'ARCH_RMOBILE' | xargs -I {} sed -i 's@ARCH_RMOBILE@ARCH_RENESAS@g' {}
"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Marek Vasut
65abdd1978 ARM: renesas: Rename rmobile.h to renesas.h
Rename rmobile.h to renesas.h because all the chips are made
by Renesas, while only a subset of them is from the R-Mobile
line.

Use the following command to perform the rename:

"
$ git grep -l 'include.*rmobile.h' | \
  xargs -I {} sed -i '/include.*rmobile.h/ s@rmobile.h@renesas.h@g' {}
"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Marek Vasut
c2cffb01aa ARM: renesas: Rename RMOBILE_CPU_TYPE_* to RENESAS_CPU_TYPE_*
Rename RMOBILE_CPU_TYPE_* to RENESAS_CPU_TYPE_* because all
the chips are made by Renesas, while only a subset of them is
from the R-Mobile line.

Use the following command to perform the rename:

"
$ git grep -l '\<RMOBILE_CPU_TYPE_[A-Z0-9]\+\>' | \
  xargs -I {} sed -i 's@\<RMOBILE\(_CPU_TYPE_[A-Z0-9]\+\)\>@RENESAS\1@g' {}
"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Marek Vasut
ca40ed6d7f ARM: renesas: Rename rmobile_get_cpu_rev_*() to renesas_get_cpu_rev_*()
Rename rmobile_get_cpu_rev_*() to renesas_get_cpu_rev_*() because
all the chips are made by Renesas, while only a subset of them is
from the R-Mobile line.

Use the following command to perform the rename:

"
$ git grep -l '\<rmobile_get_cpu_rev_\(integer\|fraction\)\>' | \
  xargs -I {} sed -i 's@\<rmobile_get_cpu_rev_\(integer\|fraction\)\>@renesas_get_cpu_rev_\1@g' {}
"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Marek Vasut
6bd3a95b67 ARM: renesas: Rename rmobile_get_cpu_type() to renesas_get_cpu_type()
Rename rmobile_get_cpu_type() to renesas_get_cpu_type() because
all the chips are made by Renesas, while only a subset of them
is from the R-Mobile line.

Use the following command to perform the rename:

"
$ git grep -l '\<rmobile_get_cpu_type\>' | \
  xargs -I {} sed -i 's@\<rmobile_get_cpu_type\>@renesas_get_cpu_type@g' {}
"

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2024-03-02 14:29:36 -05:00
Maksim Kiselev
67c7f14af3 pci-host-ecam-generic: Convert to ofnode functions
FDT functions is not working when OF_LIVE is enabled.
Convert fdt parsing functions to ofnode parsing functions

Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
2024-03-02 12:26:56 -05:00
Heinrich Schuchardt
657bd30c6b rng: eliminate common.h include from RNG drivers
Usage of common.h is deprecated.

* Remove common.h from RNG drivers.
* Sort includes.
* Add time.h to sandbox driver.
* Add linux/types.h to rng.h to provide size_t.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-03-02 12:26:19 -05:00
BELOUARGA Mohamed
e3f2493d61 net: macb: Add support for fixed link
The actual driver does not work when there is no linked PHY. These
changes add support for fixed-link feature in the device tree.

Signed-off-by: BELOUARGA Mohamed <m.belouarga@technologyandstrategy.com>
2024-03-02 12:26:18 -05:00
Weijie Gao
172e32add3 net: mediatek: add support for XGMII interface
This patch add XGMII support for connecting 2.5G PHY.

Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2024-03-01 16:35:52 -05:00
Weijie Gao
85d1968e75 net: mediatek: add support for adjusting MDIO clock
User can assign a specific MDC speed to the eth node as follow:

&eth {
	...
	phy-mode = "usxgmii";
	phy-handle = <&phy8>;

	mdio {
		clock-frequency = <10500000>;
	};

	phy8: eth-phy@8 {
	      compatible = "ethernet-phy-id31c3.1c12";
	...
};

Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2024-03-01 16:35:52 -05:00
Ivan Mikhaylov
88bb4104ad pinctrl: aspeed: add pass-through pins and siopbi/siopbo
Add THRU0-3 and SIOPBI/SIOPBO pin groups/functions.

Signed-off-by: Ivan Mikhaylov <fr0st61te@gmail.com>
2024-03-01 16:35:52 -05:00