Samsung clock drivers usually define the clock indices that are unique
per one CMU, but are not unique across all CMUs. That is, clock indices
start from 1 for each CMU, as provided in CMU bindings header. The way
the clock lookup via clk_get_by_index() works at the moment is by using
clk_of_xlate_default(), which returns globally non-unique clock ids for
for clocks registered with Samsung CCF API, which leads to incorrect
clocks being obtained. One way to fix that would be to make all clock
ids defined in the bindings header unique, but it'd make it incompatible
with Linux kernel bindings header. A better way to solve this issue is
to calculate the global clock id and use it when registering a clock
with clk_dm() and when obtaining it, in a custom .of_xlate function.
This patch adds an API for such mapping calculation, introducing the
necessary modifications to CMU registering functions in Samsung CCF.
Exynos850 clock driver (the only driver that uses Samsung CCF at the
moment) is modified accordingly, as it uses the changed API. So the
clock lookup with clk-exynos850.c driver is also fixed here.
The global clock id is calculated from CMU id and local clock id in
SAMSUNG_TO_CLK_ID() macro like this:
clk_id_global = cmu_id * 256 + clk_id_local
leaving a range of up to 256 clocks for each CMU. Then this mapping
macro is used in clk_dm() to register clocks using their global ids, and
in .of_xlate() to lookup the clock by its local id correctly. Because
.of_xlate() operation has a separate function for each CMU, it "knows"
the correct way of finding the correct clk_id_global by provided
clk_id_local.
Fixes: ff3e8b8c6c22 ("clk: exynos: Add Samsung clock framework")
Fixes: a36cc5e3ef4d ("clk: exynos: Add Exynos850 clock driver")
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Samsung CCF is meant to be used from the clock drivers by calling the
CMU registration API, i.e.:
- samsung_cmu_register_one() -- for top-level CMU
- samsung_register_cmu() -- for the rest of CMUs
Functions for registering separate clocks is probably not going to be
very useful, and isn't used at the moment. Remove prototypes of those
functions to make the Samsung CCF interface more compact and clear.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Group CMU_TOP clocks to make it easier to add the support for more CMUs.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This message is used to commit into the fuses any new SRK revocation and
FW version information that have been found into the NXP (ELE FW) and
OEM containers.
Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
Since now we have the modern pcie_dw_imx.c driver for iMX SoCs,
encourage people to switch to that for any further new iMX SoC support
or even for the older iMX6 SoCs too.
Suggested-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
pcie_imx doesn't seem to share any useful code for iMX8 SoC and it is
tied to quite old port of pcie_designware driver from Linux which
suffices only iMX6 specific needs.
But currently we have the common DWC specific bits which alligns pretty
well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
add support for other iMX8 variants to this driver.
iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
can reuse the generic PHY infrastructure to power on PCIe PHY.
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
PHY initialization moved to this standalone PHY driver.
Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver
reference commit 7559e7572c03 ("phy: Explicitly include correct DT
includes").
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Expose the high performance PLL as clock framework clock, so the
PCIe PHY can use it when there is no external refclock provided.
Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/pmdomain/imx/imx8mp-blk-ctrl.c. Use last Linux kernel driver
reference commit 7476ddfd36ac ("pmdomain: imx8mp-blk-ctrl: Convert to
platform remove callback returning void").
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Add support for GPCv2 power domains and clock handling for PCIe and
PCIe PHY.
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Add support for i.MX8MP reset controller, it has same reset IP inside
as the other iMX7 and iMX8M variants but with different module layout.
Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/reset/reset-imx7.c. Use last Linux kernel driver reference
commit bad8a8afe19f ("reset: Explicitly include correct DT includes").
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
imx7_reset_{deassert/assert}_imx* are a bit more confusing when compared
with imx*_reset_{deassert/assert}. So refactor driver to use function
names easier to understand. This shouldn't affect the functionality
though.
Suggested-by: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Add support for PCIe clocks required to enable PCIe support on
iMX8MP SoC.
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Add APIs to set a firmware_name to a rproc and boot the rproc with the
same firmware.
Clients can call rproc_set_firmware() API to set firmware_name for a rproc
whereas rproc_boot() will load the firmware set by rproc_set_firmware() to
a buffer by calling request_firmware_into_buf(). rproc_boot() will then
load the firmware file to the remote processor and start the remote
processor.
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Acked-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
The K3 J721S2 SoCs have two C71x DSP subsystems in MAIN voltage domain,
and there are no C66x DSP subsystems on these SoCs. The C71x DSP subsystem
is a slighly updated version of the C71x DSP subsystem on J721e. The
C71x DSPs are 64 bit machine with fixed and floating point DSP
operations.
Extend support to the C71x DSPs with J721S2 compatible strings.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
The K3 J721S2 SoCs have three dual-core R5F subsystems, one in MCU
voltage domain and the other two in MAIN voltage domain. These R5F
clusters are similar to the R5F clusters in J7200 SoCs.
Compatible Info is updated to support J721S2 SoCs.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Since commit cc7df0b9e8bc ("serial: lpuart: Enable IPG clock")
the apalis-imx8qm board no longer boots.
The reason is that the imx8qm clock driver does not handle the
LPUART IPG clocks inside get_rate(), set_rate() and enable() functions.
Fix the boot regression by adding the LPUART IPG entries.
Fixes: cc7df0b9e8bc ("serial: lpuart: Enable IPG clock")
Reported-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Since commit cc7df0b9e8bc ("serial: lpuart: Enable IPG clock")
the colibri-imx8qxp board no longer boots.
The reason is that the imx8qxp clock driver does not handle the
LPUART IPG clocks inside get_rate(), set_rate() and enable() functions.
Fix the boot regression by adding the LPUART IPG entries.
Fixes: cc7df0b9e8bc ("serial: lpuart: Enable IPG clock")
Reported-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Hiago De Franco <hiago.franco@toradex.com> # Toradex Colibri iMX8X
Acked-by: Sean Anderson <seanga2@gmail.com>
UFS storage often uses a 4096-byte sector size, add support for dynamic
sector sizes based loosely on the Linux implementation.
Support for dynamic sector sizes changes the types used in some
divisions, resulting in the compiler attempting to use
libgcc helpers (__aeabi_ldivmod).
Replace these divisions with calls to lldiv() to handle this correctly.
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20240320-b4-qcom-usb-v4-4-41be480172e1@linaro.org
[mkorpershoek: squashed the lldiv() fix from caleb]
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
To actually use the gadget the peripheral driver must be probed and we
must call g_dnl_clear_detach(). Otherwise acm_stdio_start() will always
fail to find a UDC on DT platforms.
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20240320-b4-qcom-usb-v4-3-41be480172e1@linaro.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Documentation:
* Avoid short reference link names in device-tree documentation.
UEFI/Video:
* Support code page 437 code points 1 - 31 used by GRUB
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Merge tag 'efi-next-20240321' of https://source.denx.de/u-boot/custodians/u-boot-efi into next
Pull request efi-next-20240321
Documentation:
* Avoid short reference link names in device-tree documentation.
UEFI/Video:
* Support code page 437 code points 1 - 31 used by GRUB
efi_console / UEFI applications (grub2, sd-boot, ...) pass UTF-8
character sequences to vidconsole which results in wrong glyphs for code
points outside of ASCII. The truetype console expects Unicode code
points and bitmap font based consoles expect code page 437 code points.
To support both convert UTF-8 to UTF-32 and pass Unicode code points in
vidconsole_ops.putc_xy(). These can be used directly in console_truetype
and after conversion to code page 437 in console_{normal,rotate}.
This fixes rendering of international, symbol and box drawing characters
used by UEFI applications.
Signed-off-by: Janne Grunau <j@jannau.net>
- A new driver in the misc to register setting from device tree. This
also provides user a clean interface and all register settings are
centralized in one place, device tree.
- Enable Agilex5 platform for Intel product. Changes, modification and
new files are created for board, dts, configs and makefile to create
the base for Agilex5.
Build-tested on SoC64 boards, boot tested on some of them.
This patch is to enable Agilex5 platform for Intel
product. Changes, modification and new files are
created for board, dts, configs and makefile to
create the base for Agilex5.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
Add socfpga_dtreg driver enablement for Intel SoCFPGA.
Signed-off-by: Wan Yee Lau <wan.yee.lau@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
The polling rate is already specified in some devicetrees, like
imx8mp.dtsi for example, but was not selected so far. For the
trippoints, the cpu-thermal node is used. Also get the polling rate from
this node. Use the default of 5000ms if the polling rate should not be
specified in the devicetree.
NOTE: The polling rate from the devicetree will be used after this
patch. In imx8*.dtsi devicetrees the polling delay is set to 2000ms for
example.
Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Please pull the updates for rockchip platform:
- Add board: rk3588 Generic, Cool Pi CM5, Theobroma-Systems RK3588 Jaguar SBC,
Toybrick TB-RK3588X;
rk3588s Cool Pi 4B;
rk3566 Pine64 PineTab2;
- Add saradc v2 support;
- Add PMIC RK806 support;
- rk3588 disable force_jtag by default;
- Migrate to use IO-domain driver for all boards;
- Use common bss and stack addresses for rk33xx and rk35xx boards;
- Other updates for driver, config and dts;
The BUTTON_ADC symbol guards the compilation of button-adc driver whose
name very well makes it explicit that it requires ADC support to be
enabled.
Fix build issue of button-adc driver when ADC support isn't enabled by
making sure it cannot be built without ADC support.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
The ADC controller drivers are obviously all depending on ADC symbol
being selected.
While they don't seem to fail to build without, they won't be useful
without that symbol selected, so let's make sure the options aren't
shown in menuconfig when ADC isn't selected.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
SPL_PMIC_RK8XX and PMIC_RK8XX both share the same prompt making it
difficult to know at first glance in menuconfig what's for what, let's
fix this by adding "in SPL" at the end of the prompt for the SPL symbol.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
This adds support for the SARADCv2 found on RK3588.
There is no stop callback as it is currently configured in single
conversion mode, where the ADC is powered down after a single conversion
has been made.
Due to what seems to be a silicon bug, a controller reset needs to be
issued before starting a channel conversion otherwise Rockchip says that
channel 1 will error whatever that means. This is aligned with upstream
and downstream Linux kernel as well as downstream U-Boot.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
SARADC v2 doesn't have a stop mechanism once in single mode. In series
conversion, the logic is different anyway. Therefore, let's abstract
this function so that it can be provided from the udevice.data pointer.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
SARADC v1 and v2 have a different way of starting a channel, therefore
let's abstract this function so that it can be provided from the
udevice.data pointer.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
SARADC v1 and v2 have a different way of reading data, therefore let's
abstract this function so that it can be provided from the udevice.data
pointer.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
The registers are entirely different between SARADC v1 and SARADC v2, so
let's prepare to add another struct for accessing v2 registers by adding
a union.
Cc: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
This adds support for RK806, only the SPI variant has been tested.
The communication "protocol" over SPI is the following:
- write three bytes:
- 1 byte: [0:3] length of the payload, [6] Enable CRC, [7] Write
- 1 byte: LSB register address
- 1 byte: MSB register address
- write/read length of payload
The CRC is always disabled for now.
The RK806 technically supports I2C as well, and this should be able to
support it without any change, but it wasn't tested.
The DT node name prefix for the buck converters has changed in the
Device Tree and is now dcdc-reg. The logic for buck converters is
however manageable within the current logic inside the rk8xx regulator
driver. The same cannot be said for the NLDO and PLDO.
Because pmic_bind_children() parses the DT nodes and extracts the LDO
index from the DT node name, NLDO and PLDO will have overlapping
indices. Therefore, we need a separate logic from the already-existing
ldo callbacks. Let's reuse as much as possible though.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
By passing a rk8xx_reg_info directly to the internal get_value, it'd be
possible to call this same function with a logic for getting the
rk8xx_reg_info different from the current get_ldo_reg, e.g. for NLDO and
PLDO support for RK806.
No logic change is expected.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
On RK809 in PMIC_POWER_ENX registers, in order to set or clear a bit N,
the bit at offset N + 4 needs to be set otherwise nothing is done.
This fixes the inability to modify the SWITCH state on RK809.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: William Wu <william.wu@rock-chips.com>
[reworded commit log]
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Those two functions had their last user removed in commit f9c68a566c4d
("rockchip: phycore_rk3288: remove phycore_init() function") part of
v2023.01 release, so let's do some cleanup here.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
The read-only mode is currently supported but only for 16b-aligned
buffers. For unaligned buffers, the last byte will be read in RW mode
right now, which isn't what is desired. Instead, let's put the
controller back into RO mode for that last byte and skip any write in
the xfer loop.
This is required for 3-wire SPI mode where PICO/POCI lanes are shorted
on HW level. This incidentally the recommended design for RK806 PMIC for
RK3588 products.
Cc: Quentin Schulz <foss+uboot@0leil.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Port the RK3399 part of the Rockchip IO-domain driver from linux.
This differs from linux version in that pmu io iodomain bit is enabled
in the write ops instead of in an init ops as in linux, this way we can
avoid keeping a full state of all supply that have been configured.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
RK3036 is using the USB product id normally used by RK3066B, and RK3328
is using the product id normally used by RK3368.
Fix this and update the default USB_GADGET_PRODUCT_NUM Kconfig option
for remaining supported Rockchip SoCs to match the product id used in
Maskrom mode.
Also remove a reference to an undefined ROCKCHIP_RK3229 Kconfig symbol.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
The USB2PHY regs already contain working default reset values for RK3328
and RK35xx as evidenced by the fact that this driver never has changed a
single value for these SoCs.
Reduce to only configure utmi_suspend_n and utmi_sel bits similar to
what is currently done on RK3399. Also add missing clkout_ctl for RK3588.
When enabled utmi_suspend_n is changed to normal mode and utmi_sel to
use otg/host controller utmi interface to phy. When disabled
utmi_suspend_n is changed to suspend mode and utmi_sel to use GRF utmi
interface to phy.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
On RK3399 the USB2PHY regs are located in the common GRF, remaining SoCs
that is supported by this driver have the USB2PHY regs in a different
GRF.
When support for RK356x, RK3588 and RK3328 was added this driver was
never updated to use correct GRF and have instead incorrectly written
to wrong GRF for these SoCs.
The default reset values for the USB2PHY have made USB mostly working
even when wrong GRF was used, however, following have been observed:
scanning bus usb@fd840000 for devices...
ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did
not provide a handshake (OUT) (5)
ERROR: USB-error: DEVICENOTRESPONDING: Device did not respond to token (IN) or did
not provide a handshake (OUT) (5)
unable to get device descriptor (error=-1)
Fix this by using a regmap from rockchip,usbgrf prop and fall back to
getting a regmap for parent udevice instead of always getting the
common GRF.
Also protect against accidental clear of bit 0 in a reg with offset 0,
only bind driver to enabled otg/host-ports and remove unused headers.
Fixes: 3da15f0b49a2 ("phy: rockchip-inno-usb2: Add USB2 PHY for rk3568")
Fixes: cdf9010f6e17 ("phy: rockchip-inno-usb2: add initial support for rk3588 PHY")
Fixes: 9aa93d84038b ("phy: rockchip-inno-usb2: Add USB2 PHY for RK3328")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Replace the rockchip,cryptov1-rng compatible with compatibles used in
the linux device tree for RK3288, RK3328 and RK3399 to ease sync of SoC
device tree from linux.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The U-Boot driver try to base the gpio bank id on the gpio-ranges prop
and fall back to base the bank id on the node name. However, the linux
driver try to base the bank id on the gpio alias id and fall back on
node order.
This can cause issues when SoC DT is synced from linux and gpioX@ nodes
has been renamed to gpio@ and gpio-ranges or a SoC specific alias has
not been assigned.
Try to use the gpio alias id as first fallback when a gpio-ranges prop
is missing to ease sync of updated SoC DT. Keep the current fallback on
node name as a third fallback to not affect any existing unsynced DT.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
