Reid Tonking c9fff93cbe arm: dts: k3-j7200-r5-common: Add msmc clk to a72 node
The j7200 SOC has a single DDR controller and hence no need for
configuring the MSMC interleaver. Hence we do not have an explicit node
for MSMC in j7200 DT, unlike j721s2/j784s4.

Also, MSMC clk id is described under A72SS0_CORE0 Device in TISCI
documentation [0].

Considering the above, define the MSMC clk in the a72 node.

[0]: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/clocks.html#clocks-for-a72ss0-core0-device

Signed-off-by: Reid Tonking <reidt@ti.com>
Signed-off-by: Aniket Limaye <a-limaye@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
2024-12-04 14:30:18 -06:00
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